1/* 2 * m32r_sio.c 3 * 4 * Driver for M32R serial ports 5 * 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * Based on drivers/serial/8250.c. 8 * 9 * Copyright (C) 2001 Russell King. 10 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 */ 17 18/* 19 * A note about mapbase / membase 20 * 21 * mapbase is the physical address of the IO port. Currently, we don't 22 * support this very well, and it may well be dropped from this driver 23 * in future. As such, mapbase should be NULL. 24 * 25 * membase is an 'ioremapped' cookie. This is compatible with the old 26 * serial.c driver, and is currently the preferred form. 27 */ 28 29#if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 30#define SUPPORT_SYSRQ 31#endif 32 33#include <linux/module.h> 34#include <linux/tty.h> 35#include <linux/ioport.h> 36#include <linux/init.h> 37#include <linux/console.h> 38#include <linux/sysrq.h> 39#include <linux/serial.h> 40#include <linux/serialP.h> 41#include <linux/delay.h> 42 43#include <asm/m32r.h> 44#include <asm/io.h> 45#include <asm/irq.h> 46 47#define PORT_M32R_BASE PORT_M32R_SIO 48#define PORT_INDEX(x) (x - PORT_M32R_BASE + 1) 49#define BAUD_RATE 115200 50 51#include <linux/serial_core.h> 52#include "m32r_sio.h" 53#include "m32r_sio_reg.h" 54 55/* 56 * Debugging. 57 */ 58#define DEBUG_AUTOCONF(fmt...) do { } while (0) 59 60#define DEBUG_INTR(fmt...) do { } while (0) 61 62#define PASS_LIMIT 256 63 64/* 65 * We default to IRQ0 for the "no irq" hack. Some 66 * machine types want others as well - they're free 67 * to redefine this in their header file. 68 */ 69#define is_real_interrupt(irq) ((irq) != 0) 70 71#define BASE_BAUD 115200 72 73/* Standard COM flags */ 74#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST) 75 76/* 77 * SERIAL_PORT_DFNS tells us about built-in ports that have no 78 * standard enumeration mechanism. Platforms that can find all 79 * serial ports via mechanisms like ACPI or PCI need not supply it. 80 */ 81#if defined(CONFIG_PLAT_USRV) 82 83#define SERIAL_PORT_DFNS \ 84 /* UART CLK PORT IRQ FLAGS */ \ 85 { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \ 86 { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */ 87 88#else /* !CONFIG_PLAT_USRV */ 89 90#if defined(CONFIG_SERIAL_M32R_PLDSIO) 91#define SERIAL_PORT_DFNS \ 92 { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \ 93 STD_COM_FLAGS }, /* ttyS0 */ 94#else 95#define SERIAL_PORT_DFNS \ 96 { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \ 97 STD_COM_FLAGS }, /* ttyS0 */ 98#endif 99 100#endif /* !CONFIG_PLAT_USRV */ 101 102static struct old_serial_port old_serial_port[] = { 103 SERIAL_PORT_DFNS 104}; 105 106#define UART_NR ARRAY_SIZE(old_serial_port) 107 108struct uart_sio_port { 109 struct uart_port port; 110 struct timer_list timer; /* "no irq" timer */ 111 struct list_head list; /* ports on this IRQ */ 112 unsigned short rev; 113 unsigned char acr; 114 unsigned char ier; 115 unsigned char lcr; 116 unsigned char mcr_mask; /* mask of user bits */ 117 unsigned char mcr_force; /* mask of forced bits */ 118 unsigned char lsr_break_flag; 119 120 /* 121 * We provide a per-port pm hook. 122 */ 123 void (*pm)(struct uart_port *port, 124 unsigned int state, unsigned int old); 125}; 126 127struct irq_info { 128 spinlock_t lock; 129 struct list_head *head; 130}; 131 132static struct irq_info irq_lists[NR_IRQS]; 133 134/* 135 * Here we define the default xmit fifo size used for each type of UART. 136 */ 137static const struct serial_uart_config uart_config[] = { 138 [PORT_UNKNOWN] = { 139 .name = "unknown", 140 .dfl_xmit_fifo_size = 1, 141 .flags = 0, 142 }, 143 [PORT_INDEX(PORT_M32R_SIO)] = { 144 .name = "M32RSIO", 145 .dfl_xmit_fifo_size = 1, 146 .flags = 0, 147 }, 148}; 149 150#ifdef CONFIG_SERIAL_M32R_PLDSIO 151 152#define __sio_in(x) inw((unsigned long)(x)) 153#define __sio_out(v,x) outw((v),(unsigned long)(x)) 154 155static inline void sio_set_baud_rate(unsigned long baud) 156{ 157 unsigned short sbaud; 158 sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1; 159 __sio_out(sbaud, PLD_ESIO0BAUR); 160} 161 162static void sio_reset(void) 163{ 164 unsigned short tmp; 165 166 tmp = __sio_in(PLD_ESIO0RXB); 167 tmp = __sio_in(PLD_ESIO0RXB); 168 tmp = __sio_in(PLD_ESIO0CR); 169 sio_set_baud_rate(BAUD_RATE); 170 __sio_out(0x0300, PLD_ESIO0CR); 171 __sio_out(0x0003, PLD_ESIO0CR); 172} 173 174static void sio_init(void) 175{ 176 unsigned short tmp; 177 178 tmp = __sio_in(PLD_ESIO0RXB); 179 tmp = __sio_in(PLD_ESIO0RXB); 180 tmp = __sio_in(PLD_ESIO0CR); 181 __sio_out(0x0300, PLD_ESIO0CR); 182 __sio_out(0x0003, PLD_ESIO0CR); 183} 184 185static void sio_error(int *status) 186{ 187 printk("SIO0 error[%04x]\n", *status); 188 do { 189 sio_init(); 190 } while ((*status = __sio_in(PLD_ESIO0CR)) != 3); 191} 192 193#else /* not CONFIG_SERIAL_M32R_PLDSIO */ 194 195#define __sio_in(x) inl(x) 196#define __sio_out(v,x) outl((v),(x)) 197 198static inline void sio_set_baud_rate(unsigned long baud) 199{ 200 unsigned long i, j; 201 202 i = boot_cpu_data.bus_clock / (baud * 16); 203 j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud; 204 i -= 1; 205 j = (j + 1) >> 1; 206 207 __sio_out(i, M32R_SIO0_BAUR_PORTL); 208 __sio_out(j, M32R_SIO0_RBAUR_PORTL); 209} 210 211static void sio_reset(void) 212{ 213 __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */ 214 __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */ 215 __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */ 216 sio_set_baud_rate(BAUD_RATE); 217 __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL); 218 __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */ 219} 220 221static void sio_init(void) 222{ 223 unsigned int tmp; 224 225 tmp = __sio_in(M32R_SIO0_RXB_PORTL); 226 tmp = __sio_in(M32R_SIO0_RXB_PORTL); 227 tmp = __sio_in(M32R_SIO0_STS_PORTL); 228 __sio_out(0x00000003, M32R_SIO0_CR_PORTL); 229} 230 231static void sio_error(int *status) 232{ 233 printk("SIO0 error[%04x]\n", *status); 234 do { 235 sio_init(); 236 } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3); 237} 238 239#endif /* CONFIG_SERIAL_M32R_PLDSIO */ 240 241static unsigned int sio_in(struct uart_sio_port *up, int offset) 242{ 243 return __sio_in(up->port.iobase + offset); 244} 245 246static void sio_out(struct uart_sio_port *up, int offset, int value) 247{ 248 __sio_out(value, up->port.iobase + offset); 249} 250 251static unsigned int serial_in(struct uart_sio_port *up, int offset) 252{ 253 if (!offset) 254 return 0; 255 256 return __sio_in(offset); 257} 258 259static void serial_out(struct uart_sio_port *up, int offset, int value) 260{ 261 if (!offset) 262 return; 263 264 __sio_out(value, offset); 265} 266 267static void m32r_sio_stop_tx(struct uart_port *port) 268{ 269 struct uart_sio_port *up = (struct uart_sio_port *)port; 270 271 if (up->ier & UART_IER_THRI) { 272 up->ier &= ~UART_IER_THRI; 273 serial_out(up, UART_IER, up->ier); 274 } 275} 276 277static void m32r_sio_start_tx(struct uart_port *port) 278{ 279#ifdef CONFIG_SERIAL_M32R_PLDSIO 280 struct uart_sio_port *up = (struct uart_sio_port *)port; 281 struct circ_buf *xmit = &up->port.state->xmit; 282 283 if (!(up->ier & UART_IER_THRI)) { 284 up->ier |= UART_IER_THRI; 285 serial_out(up, UART_IER, up->ier); 286 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 287 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 288 up->port.icount.tx++; 289 } 290 while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY); 291#else 292 struct uart_sio_port *up = (struct uart_sio_port *)port; 293 294 if (!(up->ier & UART_IER_THRI)) { 295 up->ier |= UART_IER_THRI; 296 serial_out(up, UART_IER, up->ier); 297 } 298#endif 299} 300 301static void m32r_sio_stop_rx(struct uart_port *port) 302{ 303 struct uart_sio_port *up = (struct uart_sio_port *)port; 304 305 up->ier &= ~UART_IER_RLSI; 306 up->port.read_status_mask &= ~UART_LSR_DR; 307 serial_out(up, UART_IER, up->ier); 308} 309 310static void m32r_sio_enable_ms(struct uart_port *port) 311{ 312 struct uart_sio_port *up = (struct uart_sio_port *)port; 313 314 up->ier |= UART_IER_MSI; 315 serial_out(up, UART_IER, up->ier); 316} 317 318static void receive_chars(struct uart_sio_port *up, int *status) 319{ 320 struct tty_struct *tty = up->port.state->port.tty; 321 unsigned char ch; 322 unsigned char flag; 323 int max_count = 256; 324 325 do { 326 ch = sio_in(up, SIORXB); 327 flag = TTY_NORMAL; 328 up->port.icount.rx++; 329 330 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | 331 UART_LSR_FE | UART_LSR_OE))) { 332 /* 333 * For statistics only 334 */ 335 if (*status & UART_LSR_BI) { 336 *status &= ~(UART_LSR_FE | UART_LSR_PE); 337 up->port.icount.brk++; 338 /* 339 * We do the SysRQ and SAK checking 340 * here because otherwise the break 341 * may get masked by ignore_status_mask 342 * or read_status_mask. 343 */ 344 if (uart_handle_break(&up->port)) 345 goto ignore_char; 346 } else if (*status & UART_LSR_PE) 347 up->port.icount.parity++; 348 else if (*status & UART_LSR_FE) 349 up->port.icount.frame++; 350 if (*status & UART_LSR_OE) 351 up->port.icount.overrun++; 352 353 /* 354 * Mask off conditions which should be ingored. 355 */ 356 *status &= up->port.read_status_mask; 357 358 if (up->port.line == up->port.cons->index) { 359 /* Recover the break flag from console xmit */ 360 *status |= up->lsr_break_flag; 361 up->lsr_break_flag = 0; 362 } 363 364 if (*status & UART_LSR_BI) { 365 DEBUG_INTR("handling break...."); 366 flag = TTY_BREAK; 367 } else if (*status & UART_LSR_PE) 368 flag = TTY_PARITY; 369 else if (*status & UART_LSR_FE) 370 flag = TTY_FRAME; 371 } 372 if (uart_handle_sysrq_char(&up->port, ch)) 373 goto ignore_char; 374 if ((*status & up->port.ignore_status_mask) == 0) 375 tty_insert_flip_char(tty, ch, flag); 376 377 if (*status & UART_LSR_OE) { 378 /* 379 * Overrun is special, since it's reported 380 * immediately, and doesn't affect the current 381 * character. 382 */ 383 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 384 } 385 ignore_char: 386 *status = serial_in(up, UART_LSR); 387 } while ((*status & UART_LSR_DR) && (max_count-- > 0)); 388 tty_flip_buffer_push(tty); 389} 390 391static void transmit_chars(struct uart_sio_port *up) 392{ 393 struct circ_buf *xmit = &up->port.state->xmit; 394 int count; 395 396 if (up->port.x_char) { 397#ifndef CONFIG_SERIAL_M32R_PLDSIO 398 serial_out(up, UART_TX, up->port.x_char); 399#endif 400 up->port.icount.tx++; 401 up->port.x_char = 0; 402 return; 403 } 404 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 405 m32r_sio_stop_tx(&up->port); 406 return; 407 } 408 409 count = up->port.fifosize; 410 do { 411 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 412 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 413 up->port.icount.tx++; 414 if (uart_circ_empty(xmit)) 415 break; 416 while (!(serial_in(up, UART_LSR) & UART_LSR_THRE)); 417 418 } while (--count > 0); 419 420 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 421 uart_write_wakeup(&up->port); 422 423 DEBUG_INTR("THRE..."); 424 425 if (uart_circ_empty(xmit)) 426 m32r_sio_stop_tx(&up->port); 427} 428 429/* 430 * This handles the interrupt from one port. 431 */ 432static inline void m32r_sio_handle_port(struct uart_sio_port *up, 433 unsigned int status) 434{ 435 DEBUG_INTR("status = %x...", status); 436 437 if (status & 0x04) 438 receive_chars(up, &status); 439 if (status & 0x01) 440 transmit_chars(up); 441} 442 443/* 444 * This is the serial driver's interrupt routine. 445 * 446 * Arjan thinks the old way was overly complex, so it got simplified. 447 * Alan disagrees, saying that need the complexity to handle the weird 448 * nature of ISA shared interrupts. (This is a special exception.) 449 * 450 * In order to handle ISA shared interrupts properly, we need to check 451 * that all ports have been serviced, and therefore the ISA interrupt 452 * line has been de-asserted. 453 * 454 * This means we need to loop through all ports. checking that they 455 * don't have an interrupt pending. 456 */ 457static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id) 458{ 459 struct irq_info *i = dev_id; 460 struct list_head *l, *end = NULL; 461 int pass_counter = 0; 462 463 DEBUG_INTR("m32r_sio_interrupt(%d)...", irq); 464 465#ifdef CONFIG_SERIAL_M32R_PLDSIO 466// if (irq == PLD_IRQ_SIO0_SND) 467// irq = PLD_IRQ_SIO0_RCV; 468#else 469 if (irq == M32R_IRQ_SIO0_S) 470 irq = M32R_IRQ_SIO0_R; 471#endif 472 473 spin_lock(&i->lock); 474 475 l = i->head; 476 do { 477 struct uart_sio_port *up; 478 unsigned int sts; 479 480 up = list_entry(l, struct uart_sio_port, list); 481 482 sts = sio_in(up, SIOSTS); 483 if (sts & 0x5) { 484 spin_lock(&up->port.lock); 485 m32r_sio_handle_port(up, sts); 486 spin_unlock(&up->port.lock); 487 488 end = NULL; 489 } else if (end == NULL) 490 end = l; 491 492 l = l->next; 493 494 if (l == i->head && pass_counter++ > PASS_LIMIT) { 495 if (sts & 0xe0) 496 sio_error(&sts); 497 break; 498 } 499 } while (l != end); 500 501 spin_unlock(&i->lock); 502 503 DEBUG_INTR("end.\n"); 504 505 return IRQ_HANDLED; 506} 507 508/* 509 * To support ISA shared interrupts, we need to have one interrupt 510 * handler that ensures that the IRQ line has been deasserted 511 * before returning. Failing to do this will result in the IRQ 512 * line being stuck active, and, since ISA irqs are edge triggered, 513 * no more IRQs will be seen. 514 */ 515static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up) 516{ 517 spin_lock_irq(&i->lock); 518 519 if (!list_empty(i->head)) { 520 if (i->head == &up->list) 521 i->head = i->head->next; 522 list_del(&up->list); 523 } else { 524 BUG_ON(i->head != &up->list); 525 i->head = NULL; 526 } 527 528 spin_unlock_irq(&i->lock); 529} 530 531static int serial_link_irq_chain(struct uart_sio_port *up) 532{ 533 struct irq_info *i = irq_lists + up->port.irq; 534 int ret, irq_flags = 0; 535 536 spin_lock_irq(&i->lock); 537 538 if (i->head) { 539 list_add(&up->list, i->head); 540 spin_unlock_irq(&i->lock); 541 542 ret = 0; 543 } else { 544 INIT_LIST_HEAD(&up->list); 545 i->head = &up->list; 546 spin_unlock_irq(&i->lock); 547 548 ret = request_irq(up->port.irq, m32r_sio_interrupt, 549 irq_flags, "SIO0-RX", i); 550 ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt, 551 irq_flags, "SIO0-TX", i); 552 if (ret < 0) 553 serial_do_unlink(i, up); 554 } 555 556 return ret; 557} 558 559static void serial_unlink_irq_chain(struct uart_sio_port *up) 560{ 561 struct irq_info *i = irq_lists + up->port.irq; 562 563 BUG_ON(i->head == NULL); 564 565 if (list_empty(i->head)) { 566 free_irq(up->port.irq, i); 567 free_irq(up->port.irq + 1, i); 568 } 569 570 serial_do_unlink(i, up); 571} 572 573/* 574 * This function is used to handle ports that do not have an interrupt. 575 */ 576static void m32r_sio_timeout(unsigned long data) 577{ 578 struct uart_sio_port *up = (struct uart_sio_port *)data; 579 unsigned int timeout; 580 unsigned int sts; 581 582 sts = sio_in(up, SIOSTS); 583 if (sts & 0x5) { 584 spin_lock(&up->port.lock); 585 m32r_sio_handle_port(up, sts); 586 spin_unlock(&up->port.lock); 587 } 588 589 timeout = up->port.timeout; 590 timeout = timeout > 6 ? (timeout / 2 - 2) : 1; 591 mod_timer(&up->timer, jiffies + timeout); 592} 593 594static unsigned int m32r_sio_tx_empty(struct uart_port *port) 595{ 596 struct uart_sio_port *up = (struct uart_sio_port *)port; 597 unsigned long flags; 598 unsigned int ret; 599 600 spin_lock_irqsave(&up->port.lock, flags); 601 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 602 spin_unlock_irqrestore(&up->port.lock, flags); 603 604 return ret; 605} 606 607static unsigned int m32r_sio_get_mctrl(struct uart_port *port) 608{ 609 return 0; 610} 611 612static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl) 613{ 614 615} 616 617static void m32r_sio_break_ctl(struct uart_port *port, int break_state) 618{ 619 620} 621 622static int m32r_sio_startup(struct uart_port *port) 623{ 624 struct uart_sio_port *up = (struct uart_sio_port *)port; 625 int retval; 626 627 sio_init(); 628 629 /* 630 * If the "interrupt" for this port doesn't correspond with any 631 * hardware interrupt, we use a timer-based system. The original 632 * driver used to do this with IRQ0. 633 */ 634 if (!is_real_interrupt(up->port.irq)) { 635 unsigned int timeout = up->port.timeout; 636 637 timeout = timeout > 6 ? (timeout / 2 - 2) : 1; 638 639 up->timer.data = (unsigned long)up; 640 mod_timer(&up->timer, jiffies + timeout); 641 } else { 642 retval = serial_link_irq_chain(up); 643 if (retval) 644 return retval; 645 } 646 647 /* 648 * Finally, enable interrupts. Note: Modem status interrupts 649 * are set via set_termios(), which will be occurring imminently 650 * anyway, so we don't enable them here. 651 * - M32R_SIO: 0x0c 652 * - M32R_PLDSIO: 0x04 653 */ 654 up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; 655 sio_out(up, SIOTRCR, up->ier); 656 657 /* 658 * And clear the interrupt registers again for luck. 659 */ 660 sio_reset(); 661 662 return 0; 663} 664 665static void m32r_sio_shutdown(struct uart_port *port) 666{ 667 struct uart_sio_port *up = (struct uart_sio_port *)port; 668 669 /* 670 * Disable interrupts from this port 671 */ 672 up->ier = 0; 673 sio_out(up, SIOTRCR, 0); 674 675 /* 676 * Disable break condition and FIFOs 677 */ 678 679 sio_init(); 680 681 if (!is_real_interrupt(up->port.irq)) 682 del_timer_sync(&up->timer); 683 else 684 serial_unlink_irq_chain(up); 685} 686 687static unsigned int m32r_sio_get_divisor(struct uart_port *port, 688 unsigned int baud) 689{ 690 return uart_get_divisor(port, baud); 691} 692 693static void m32r_sio_set_termios(struct uart_port *port, 694 struct ktermios *termios, struct ktermios *old) 695{ 696 struct uart_sio_port *up = (struct uart_sio_port *)port; 697 unsigned char cval = 0; 698 unsigned long flags; 699 unsigned int baud, quot; 700 701 switch (termios->c_cflag & CSIZE) { 702 case CS5: 703 cval = UART_LCR_WLEN5; 704 break; 705 case CS6: 706 cval = UART_LCR_WLEN6; 707 break; 708 case CS7: 709 cval = UART_LCR_WLEN7; 710 break; 711 default: 712 case CS8: 713 cval = UART_LCR_WLEN8; 714 break; 715 } 716 717 if (termios->c_cflag & CSTOPB) 718 cval |= UART_LCR_STOP; 719 if (termios->c_cflag & PARENB) 720 cval |= UART_LCR_PARITY; 721 if (!(termios->c_cflag & PARODD)) 722 cval |= UART_LCR_EPAR; 723#ifdef CMSPAR 724 if (termios->c_cflag & CMSPAR) 725 cval |= UART_LCR_SPAR; 726#endif 727 728 /* 729 * Ask the core to calculate the divisor for us. 730 */ 731#ifdef CONFIG_SERIAL_M32R_PLDSIO 732 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4); 733#else 734 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 735#endif 736 quot = m32r_sio_get_divisor(port, baud); 737 738 /* 739 * Ok, we're now changing the port state. Do it with 740 * interrupts disabled. 741 */ 742 spin_lock_irqsave(&up->port.lock, flags); 743 744 sio_set_baud_rate(baud); 745 746 /* 747 * Update the per-port timeout. 748 */ 749 uart_update_timeout(port, termios->c_cflag, baud); 750 751 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 752 if (termios->c_iflag & INPCK) 753 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 754 if (termios->c_iflag & (BRKINT | PARMRK)) 755 up->port.read_status_mask |= UART_LSR_BI; 756 757 /* 758 * Characteres to ignore 759 */ 760 up->port.ignore_status_mask = 0; 761 if (termios->c_iflag & IGNPAR) 762 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 763 if (termios->c_iflag & IGNBRK) { 764 up->port.ignore_status_mask |= UART_LSR_BI; 765 /* 766 * If we're ignoring parity and break indicators, 767 * ignore overruns too (for real raw support). 768 */ 769 if (termios->c_iflag & IGNPAR) 770 up->port.ignore_status_mask |= UART_LSR_OE; 771 } 772 773 /* 774 * ignore all characters if CREAD is not set 775 */ 776 if ((termios->c_cflag & CREAD) == 0) 777 up->port.ignore_status_mask |= UART_LSR_DR; 778 779 /* 780 * CTS flow control flag and modem status interrupts 781 */ 782 up->ier &= ~UART_IER_MSI; 783 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 784 up->ier |= UART_IER_MSI; 785 786 serial_out(up, UART_IER, up->ier); 787 788 up->lcr = cval; /* Save LCR */ 789 spin_unlock_irqrestore(&up->port.lock, flags); 790} 791 792static void m32r_sio_pm(struct uart_port *port, unsigned int state, 793 unsigned int oldstate) 794{ 795 struct uart_sio_port *up = (struct uart_sio_port *)port; 796 797 if (up->pm) 798 up->pm(port, state, oldstate); 799} 800 801/* 802 * Resource handling. This is complicated by the fact that resources 803 * depend on the port type. Maybe we should be claiming the standard 804 * 8250 ports, and then trying to get other resources as necessary? 805 */ 806static int 807m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res) 808{ 809 unsigned int size = 8 << up->port.regshift; 810#ifndef CONFIG_SERIAL_M32R_PLDSIO 811 unsigned long start; 812#endif 813 int ret = 0; 814 815 switch (up->port.iotype) { 816 case UPIO_MEM: 817 if (up->port.mapbase) { 818#ifdef CONFIG_SERIAL_M32R_PLDSIO 819 *res = request_mem_region(up->port.mapbase, size, "serial"); 820#else 821 start = up->port.mapbase; 822 *res = request_mem_region(start, size, "serial"); 823#endif 824 if (!*res) 825 ret = -EBUSY; 826 } 827 break; 828 829 case UPIO_PORT: 830 *res = request_region(up->port.iobase, size, "serial"); 831 if (!*res) 832 ret = -EBUSY; 833 break; 834 } 835 return ret; 836} 837 838static void m32r_sio_release_port(struct uart_port *port) 839{ 840 struct uart_sio_port *up = (struct uart_sio_port *)port; 841 unsigned long start, offset = 0, size = 0; 842 843 size <<= up->port.regshift; 844 845 switch (up->port.iotype) { 846 case UPIO_MEM: 847 if (up->port.mapbase) { 848 /* 849 * Unmap the area. 850 */ 851 iounmap(up->port.membase); 852 up->port.membase = NULL; 853 854 start = up->port.mapbase; 855 856 if (size) 857 release_mem_region(start + offset, size); 858 release_mem_region(start, 8 << up->port.regshift); 859 } 860 break; 861 862 case UPIO_PORT: 863 start = up->port.iobase; 864 865 if (size) 866 release_region(start + offset, size); 867 release_region(start + offset, 8 << up->port.regshift); 868 break; 869 870 default: 871 break; 872 } 873} 874 875static int m32r_sio_request_port(struct uart_port *port) 876{ 877 struct uart_sio_port *up = (struct uart_sio_port *)port; 878 struct resource *res = NULL; 879 int ret = 0; 880 881 ret = m32r_sio_request_std_resource(up, &res); 882 883 /* 884 * If we have a mapbase, then request that as well. 885 */ 886 if (ret == 0 && up->port.flags & UPF_IOREMAP) { 887 int size = res->end - res->start + 1; 888 889 up->port.membase = ioremap(up->port.mapbase, size); 890 if (!up->port.membase) 891 ret = -ENOMEM; 892 } 893 894 if (ret < 0) { 895 if (res) 896 release_resource(res); 897 } 898 899 return ret; 900} 901 902static void m32r_sio_config_port(struct uart_port *port, int flags) 903{ 904 struct uart_sio_port *up = (struct uart_sio_port *)port; 905 906 spin_lock_irqsave(&up->port.lock, flags); 907 908 up->port.type = (PORT_M32R_SIO - PORT_M32R_BASE + 1); 909 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size; 910 911 spin_unlock_irqrestore(&up->port.lock, flags); 912} 913 914static int 915m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser) 916{ 917 if (ser->irq >= nr_irqs || ser->irq < 0 || 918 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || 919 ser->type >= ARRAY_SIZE(uart_config)) 920 return -EINVAL; 921 return 0; 922} 923 924static const char * 925m32r_sio_type(struct uart_port *port) 926{ 927 int type = port->type; 928 929 if (type >= ARRAY_SIZE(uart_config)) 930 type = 0; 931 return uart_config[type].name; 932} 933 934static struct uart_ops m32r_sio_pops = { 935 .tx_empty = m32r_sio_tx_empty, 936 .set_mctrl = m32r_sio_set_mctrl, 937 .get_mctrl = m32r_sio_get_mctrl, 938 .stop_tx = m32r_sio_stop_tx, 939 .start_tx = m32r_sio_start_tx, 940 .stop_rx = m32r_sio_stop_rx, 941 .enable_ms = m32r_sio_enable_ms, 942 .break_ctl = m32r_sio_break_ctl, 943 .startup = m32r_sio_startup, 944 .shutdown = m32r_sio_shutdown, 945 .set_termios = m32r_sio_set_termios, 946 .pm = m32r_sio_pm, 947 .type = m32r_sio_type, 948 .release_port = m32r_sio_release_port, 949 .request_port = m32r_sio_request_port, 950 .config_port = m32r_sio_config_port, 951 .verify_port = m32r_sio_verify_port, 952}; 953 954static struct uart_sio_port m32r_sio_ports[UART_NR]; 955 956static void __init m32r_sio_init_ports(void) 957{ 958 struct uart_sio_port *up; 959 static int first = 1; 960 int i; 961 962 if (!first) 963 return; 964 first = 0; 965 966 for (i = 0, up = m32r_sio_ports; i < ARRAY_SIZE(old_serial_port); 967 i++, up++) { 968 up->port.iobase = old_serial_port[i].port; 969 up->port.irq = irq_canonicalize(old_serial_port[i].irq); 970 up->port.uartclk = old_serial_port[i].baud_base * 16; 971 up->port.flags = old_serial_port[i].flags; 972 up->port.membase = old_serial_port[i].iomem_base; 973 up->port.iotype = old_serial_port[i].io_type; 974 up->port.regshift = old_serial_port[i].iomem_reg_shift; 975 up->port.ops = &m32r_sio_pops; 976 } 977} 978 979static void __init m32r_sio_register_ports(struct uart_driver *drv) 980{ 981 int i; 982 983 m32r_sio_init_ports(); 984 985 for (i = 0; i < UART_NR; i++) { 986 struct uart_sio_port *up = &m32r_sio_ports[i]; 987 988 up->port.line = i; 989 up->port.ops = &m32r_sio_pops; 990 init_timer(&up->timer); 991 up->timer.function = m32r_sio_timeout; 992 993 /* 994 * ALPHA_KLUDGE_MCR needs to be killed. 995 */ 996 up->mcr_mask = ~ALPHA_KLUDGE_MCR; 997 up->mcr_force = ALPHA_KLUDGE_MCR; 998 999 uart_add_one_port(drv, &up->port); 1000 } 1001} 1002 1003#ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE 1004 1005/* 1006 * Wait for transmitter & holding register to empty 1007 */ 1008static inline void wait_for_xmitr(struct uart_sio_port *up) 1009{ 1010 unsigned int status, tmout = 10000; 1011 1012 /* Wait up to 10ms for the character(s) to be sent. */ 1013 do { 1014 status = sio_in(up, SIOSTS); 1015 1016 if (--tmout == 0) 1017 break; 1018 udelay(1); 1019 } while ((status & UART_EMPTY) != UART_EMPTY); 1020 1021 /* Wait up to 1s for flow control if necessary */ 1022 if (up->port.flags & UPF_CONS_FLOW) { 1023 tmout = 1000000; 1024 while (--tmout) 1025 udelay(1); 1026 } 1027} 1028 1029static void m32r_sio_console_putchar(struct uart_port *port, int ch) 1030{ 1031 struct uart_sio_port *up = (struct uart_sio_port *)port; 1032 1033 wait_for_xmitr(up); 1034 sio_out(up, SIOTXB, ch); 1035} 1036 1037/* 1038 * Print a string to the serial port trying not to disturb 1039 * any possible real use of the port... 1040 * 1041 * The console_lock must be held when we get here. 1042 */ 1043static void m32r_sio_console_write(struct console *co, const char *s, 1044 unsigned int count) 1045{ 1046 struct uart_sio_port *up = &m32r_sio_ports[co->index]; 1047 unsigned int ier; 1048 1049 /* 1050 * First save the UER then disable the interrupts 1051 */ 1052 ier = sio_in(up, SIOTRCR); 1053 sio_out(up, SIOTRCR, 0); 1054 1055 uart_console_write(&up->port, s, count, m32r_sio_console_putchar); 1056 1057 /* 1058 * Finally, wait for transmitter to become empty 1059 * and restore the IER 1060 */ 1061 wait_for_xmitr(up); 1062 sio_out(up, SIOTRCR, ier); 1063} 1064 1065static int __init m32r_sio_console_setup(struct console *co, char *options) 1066{ 1067 struct uart_port *port; 1068 int baud = 9600; 1069 int bits = 8; 1070 int parity = 'n'; 1071 int flow = 'n'; 1072 1073 /* 1074 * Check whether an invalid uart number has been specified, and 1075 * if so, search for the first available port that does have 1076 * console support. 1077 */ 1078 if (co->index >= UART_NR) 1079 co->index = 0; 1080 port = &m32r_sio_ports[co->index].port; 1081 1082 /* 1083 * Temporary fix. 1084 */ 1085 spin_lock_init(&port->lock); 1086 1087 if (options) 1088 uart_parse_options(options, &baud, &parity, &bits, &flow); 1089 1090 return uart_set_options(port, co, baud, parity, bits, flow); 1091} 1092 1093static struct uart_driver m32r_sio_reg; 1094static struct console m32r_sio_console = { 1095 .name = "ttyS", 1096 .write = m32r_sio_console_write, 1097 .device = uart_console_device, 1098 .setup = m32r_sio_console_setup, 1099 .flags = CON_PRINTBUFFER, 1100 .index = -1, 1101 .data = &m32r_sio_reg, 1102}; 1103 1104static int __init m32r_sio_console_init(void) 1105{ 1106 sio_reset(); 1107 sio_init(); 1108 m32r_sio_init_ports(); 1109 register_console(&m32r_sio_console); 1110 return 0; 1111} 1112console_initcall(m32r_sio_console_init); 1113 1114#define M32R_SIO_CONSOLE &m32r_sio_console 1115#else 1116#define M32R_SIO_CONSOLE NULL 1117#endif 1118 1119static struct uart_driver m32r_sio_reg = { 1120 .owner = THIS_MODULE, 1121 .driver_name = "sio", 1122 .dev_name = "ttyS", 1123 .major = TTY_MAJOR, 1124 .minor = 64, 1125 .nr = UART_NR, 1126 .cons = M32R_SIO_CONSOLE, 1127}; 1128 1129/** 1130 * m32r_sio_suspend_port - suspend one serial port 1131 * @line: serial line number 1132 * 1133 * Suspend one serial port. 1134 */ 1135void m32r_sio_suspend_port(int line) 1136{ 1137 uart_suspend_port(&m32r_sio_reg, &m32r_sio_ports[line].port); 1138} 1139 1140/** 1141 * m32r_sio_resume_port - resume one serial port 1142 * @line: serial line number 1143 * 1144 * Resume one serial port. 1145 */ 1146void m32r_sio_resume_port(int line) 1147{ 1148 uart_resume_port(&m32r_sio_reg, &m32r_sio_ports[line].port); 1149} 1150 1151static int __init m32r_sio_init(void) 1152{ 1153 int ret, i; 1154 1155 printk(KERN_INFO "Serial: M32R SIO driver\n"); 1156 1157 for (i = 0; i < nr_irqs; i++) 1158 spin_lock_init(&irq_lists[i].lock); 1159 1160 ret = uart_register_driver(&m32r_sio_reg); 1161 if (ret >= 0) 1162 m32r_sio_register_ports(&m32r_sio_reg); 1163 1164 return ret; 1165} 1166 1167static void __exit m32r_sio_exit(void) 1168{ 1169 int i; 1170 1171 for (i = 0; i < UART_NR; i++) 1172 uart_remove_one_port(&m32r_sio_reg, &m32r_sio_ports[i].port); 1173 1174 uart_unregister_driver(&m32r_sio_reg); 1175} 1176 1177module_init(m32r_sio_init); 1178module_exit(m32r_sio_exit); 1179 1180EXPORT_SYMBOL(m32r_sio_suspend_port); 1181EXPORT_SYMBOL(m32r_sio_resume_port); 1182 1183MODULE_LICENSE("GPL"); 1184MODULE_DESCRIPTION("Generic M32R SIO serial driver"); 1185