Searched refs:SIC_ISR1 (Results 1 - 16 of 16) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h44 #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
45 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
46 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
47 #define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
H A DdefBF539.h43 #define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ macro
1478 /* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h44 #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
45 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
46 #define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0))
47 #define bfin_write_SIC_ISR(x, val) bfin_write32(SIC_ISR0 + x * (SIC_ISR1 - SIC_ISR0), val)
H A DdefBF539.h43 #define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ macro
1478 /* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h76 #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
77 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
H A DdefBF51x_base.h42 #define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h76 #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
77 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
H A DdefBF52x_base.h45 #define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h76 #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
77 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
H A DdefBF51x_base.h42 #define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h76 #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
77 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
H A DdefBF52x_base.h45 #define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h42 #define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */ macro
1545 /* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
H A DcdefBF54x_base.h54 #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
55 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h42 #define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */ macro
1545 /* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
H A DcdefBF54x_base.h54 #define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
55 #define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)

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