1/* 2 * Copyright 2008-2009 Analog Devices Inc. 3 * 4 * Licensed under the ADI BSD license or the GPL-2 (or later) 5 */ 6 7/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF538/9 */ 8 9#ifndef _DEF_BF539_H 10#define _DEF_BF539_H 11 12/* include all Core registers and bit definitions */ 13#include <asm/def_LPBlackfin.h> 14 15 16/*********************************************************************************** */ 17/* System MMR Register Map */ 18/*********************************************************************************** */ 19/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */ 20#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ 21#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ 22#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ 23#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ 24#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ 25#define CHIPID 0xFFC00014 /* Chip ID Register */ 26 27/* CHIPID Masks */ 28#define CHIPID_VERSION 0xF0000000 29#define CHIPID_FAMILY 0x0FFFF000 30#define CHIPID_MANUFACTURE 0x00000FFE 31 32/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 33#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ 34#define SYSCR 0xFFC00104 /* System Configuration registe */ 35#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ 36#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ 37#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ 38#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ 39#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ 40#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ 41#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ 42#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */ 43#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */ 44#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */ 45#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */ 46#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */ 47#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */ 48 49 50/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ 51#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ 52#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ 53#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ 54 55 56/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ 57#define RTC_STAT 0xFFC00300 /* RTC Status Register */ 58#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ 59#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ 60#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ 61#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ 62#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ 63#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ 64 65 66/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */ 67#define UART0_THR 0xFFC00400 /* Transmit Holding register */ 68#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ 69#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ 70#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ 71#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ 72#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ 73#define UART0_LCR 0xFFC0040C /* Line Control Register */ 74#define UART0_MCR 0xFFC00410 /* Modem Control Register */ 75#define UART0_LSR 0xFFC00414 /* Line Status Register */ 76#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ 77#define UART0_GCTL 0xFFC00424 /* Global Control Register */ 78 79 80/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */ 81 82#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ 83#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ 84#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ 85#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ 86#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ 87#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ 88#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ 89#define SPI0_REGBASE SPI0_CTL 90 91 92/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ 93#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ 94#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ 95#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ 96#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ 97 98#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ 99#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ 100#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ 101#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ 102 103#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ 104#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ 105#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ 106#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ 107 108#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ 109#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ 110#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ 111 112 113/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */ 114#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ 115#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ 116#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ 117#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ 118#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ 119#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ 120#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ 121#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ 122#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ 123#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ 124#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ 125#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ 126#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ 127#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ 128#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ 129#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ 130#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ 131 132 133/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ 134#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ 135#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ 136#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ 137#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ 138#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ 139#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ 140#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ 141#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ 142#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ 143#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ 144#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ 145#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 146#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ 147#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ 148#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ 149#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ 150#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ 151#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ 152#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ 153#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ 154#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ 155#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ 156 157 158/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ 159#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ 160#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ 161#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ 162#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ 163#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ 164#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ 165#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ 166#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ 167#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ 168#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ 169#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ 170#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 171#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ 172#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ 173#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ 174#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ 175#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ 176#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ 177#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ 178#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ 179#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ 180#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ 181 182 183/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ 184/* Asynchronous Memory Controller */ 185#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ 186#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ 187#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ 188 189/* SDRAM Controller */ 190#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ 191#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ 192#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ 193#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 194 195 196 197/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */ 198 199#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */ 200#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */ 201 202/* Alternate deprecated register names (below) provided for backwards code compatibility */ 203#define DMA0_TCPER DMAC0_TC_PER 204#define DMA0_TCCNT DMAC0_TC_CNT 205 206 207/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */ 208 209#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 210#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ 211#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ 212#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ 213#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ 214#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ 215#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ 216#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ 217#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ 218#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ 219#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ 220#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ 221#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ 222 223#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ 224#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ 225#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ 226#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ 227#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ 228#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ 229#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ 230#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ 231#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ 232#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ 233#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ 234#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ 235#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ 236 237#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ 238#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ 239#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ 240#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ 241#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ 242#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ 243#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ 244#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ 245#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ 246#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ 247#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ 248#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ 249#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ 250 251#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ 252#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ 253#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ 254#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ 255#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ 256#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ 257#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ 258#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ 259#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ 260#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ 261#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ 262#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ 263#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ 264 265#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ 266#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ 267#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ 268#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ 269#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ 270#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ 271#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ 272#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ 273#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ 274#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ 275#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ 276#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ 277#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ 278 279#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ 280#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ 281#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ 282#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ 283#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ 284#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ 285#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ 286#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ 287#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ 288#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ 289#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ 290#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ 291#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ 292 293#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ 294#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ 295#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ 296#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ 297#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ 298#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ 299#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ 300#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ 301#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ 302#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ 303#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ 304#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ 305#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ 306 307#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ 308#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ 309#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ 310#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ 311#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ 312#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ 313#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ 314#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ 315#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ 316#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ 317#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ 318#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ 319#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ 320 321#define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */ 322#define MDMA0_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */ 323#define MDMA0_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */ 324#define MDMA0_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */ 325#define MDMA0_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */ 326#define MDMA0_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */ 327#define MDMA0_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */ 328#define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */ 329#define MDMA0_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */ 330#define MDMA0_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */ 331#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */ 332#define MDMA0_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */ 333#define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */ 334 335#define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */ 336#define MDMA0_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */ 337#define MDMA0_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */ 338#define MDMA0_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */ 339#define MDMA0_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */ 340#define MDMA0_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */ 341#define MDMA0_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */ 342#define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */ 343#define MDMA0_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */ 344#define MDMA0_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */ 345#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */ 346#define MDMA0_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */ 347#define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */ 348 349#define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */ 350#define MDMA0_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */ 351#define MDMA0_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */ 352#define MDMA0_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */ 353#define MDMA0_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */ 354#define MDMA0_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */ 355#define MDMA0_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */ 356#define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */ 357#define MDMA0_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */ 358#define MDMA0_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */ 359#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */ 360#define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */ 361#define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */ 362 363#define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */ 364#define MDMA0_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */ 365#define MDMA0_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */ 366#define MDMA0_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */ 367#define MDMA0_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */ 368#define MDMA0_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */ 369#define MDMA0_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */ 370#define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */ 371#define MDMA0_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */ 372#define MDMA0_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */ 373#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */ 374#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */ 375#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */ 376 377#define MDMA_D0_NEXT_DESC_PTR MDMA0_D0_NEXT_DESC_PTR 378#define MDMA_D0_START_ADDR MDMA0_D0_START_ADDR 379#define MDMA_D0_CONFIG MDMA0_D0_CONFIG 380#define MDMA_D0_X_COUNT MDMA0_D0_X_COUNT 381#define MDMA_D0_X_MODIFY MDMA0_D0_X_MODIFY 382#define MDMA_D0_Y_COUNT MDMA0_D0_Y_COUNT 383#define MDMA_D0_Y_MODIFY MDMA0_D0_Y_MODIFY 384#define MDMA_D0_CURR_DESC_PTR MDMA0_D0_CURR_DESC_PTR 385#define MDMA_D0_CURR_ADDR MDMA0_D0_CURR_ADDR 386#define MDMA_D0_IRQ_STATUS MDMA0_D0_IRQ_STATUS 387#define MDMA_D0_PERIPHERAL_MAP MDMA0_D0_PERIPHERAL_MAP 388#define MDMA_D0_CURR_X_COUNT MDMA0_D0_CURR_X_COUNT 389#define MDMA_D0_CURR_Y_COUNT MDMA0_D0_CURR_Y_COUNT 390 391#define MDMA_S0_NEXT_DESC_PTR MDMA0_S0_NEXT_DESC_PTR 392#define MDMA_S0_START_ADDR MDMA0_S0_START_ADDR 393#define MDMA_S0_CONFIG MDMA0_S0_CONFIG 394#define MDMA_S0_X_COUNT MDMA0_S0_X_COUNT 395#define MDMA_S0_X_MODIFY MDMA0_S0_X_MODIFY 396#define MDMA_S0_Y_COUNT MDMA0_S0_Y_COUNT 397#define MDMA_S0_Y_MODIFY MDMA0_S0_Y_MODIFY 398#define MDMA_S0_CURR_DESC_PTR MDMA0_S0_CURR_DESC_PTR 399#define MDMA_S0_CURR_ADDR MDMA0_S0_CURR_ADDR 400#define MDMA_S0_IRQ_STATUS MDMA0_S0_IRQ_STATUS 401#define MDMA_S0_PERIPHERAL_MAP MDMA0_S0_PERIPHERAL_MAP 402#define MDMA_S0_CURR_X_COUNT MDMA0_S0_CURR_X_COUNT 403#define MDMA_S0_CURR_Y_COUNT MDMA0_S0_CURR_Y_COUNT 404 405#define MDMA_D1_NEXT_DESC_PTR MDMA0_D1_NEXT_DESC_PTR 406#define MDMA_D1_START_ADDR MDMA0_D1_START_ADDR 407#define MDMA_D1_CONFIG MDMA0_D1_CONFIG 408#define MDMA_D1_X_COUNT MDMA0_D1_X_COUNT 409#define MDMA_D1_X_MODIFY MDMA0_D1_X_MODIFY 410#define MDMA_D1_Y_COUNT MDMA0_D1_Y_COUNT 411#define MDMA_D1_Y_MODIFY MDMA0_D1_Y_MODIFY 412#define MDMA_D1_CURR_DESC_PTR MDMA0_D1_CURR_DESC_PTR 413#define MDMA_D1_CURR_ADDR MDMA0_D1_CURR_ADDR 414#define MDMA_D1_IRQ_STATUS MDMA0_D1_IRQ_STATUS 415#define MDMA_D1_PERIPHERAL_MAP MDMA0_D1_PERIPHERAL_MAP 416#define MDMA_D1_CURR_X_COUNT MDMA0_D1_CURR_X_COUNT 417#define MDMA_D1_CURR_Y_COUNT MDMA0_D1_CURR_Y_COUNT 418 419#define MDMA_S1_NEXT_DESC_PTR MDMA0_S1_NEXT_DESC_PTR 420#define MDMA_S1_START_ADDR MDMA0_S1_START_ADDR 421#define MDMA_S1_CONFIG MDMA0_S1_CONFIG 422#define MDMA_S1_X_COUNT MDMA0_S1_X_COUNT 423#define MDMA_S1_X_MODIFY MDMA0_S1_X_MODIFY 424#define MDMA_S1_Y_COUNT MDMA0_S1_Y_COUNT 425#define MDMA_S1_Y_MODIFY MDMA0_S1_Y_MODIFY 426#define MDMA_S1_CURR_DESC_PTR MDMA0_S1_CURR_DESC_PTR 427#define MDMA_S1_CURR_ADDR MDMA0_S1_CURR_ADDR 428#define MDMA_S1_IRQ_STATUS MDMA0_S1_IRQ_STATUS 429#define MDMA_S1_PERIPHERAL_MAP MDMA0_S1_PERIPHERAL_MAP 430#define MDMA_S1_CURR_X_COUNT MDMA0_S1_CURR_X_COUNT 431#define MDMA_S1_CURR_Y_COUNT MDMA0_S1_CURR_Y_COUNT 432 433 434/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ 435#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ 436#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ 437#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ 438#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ 439#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ 440 441 442/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */ 443#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 444#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */ 445#define TWI0_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 446#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ 447#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ 448#define TWI0_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ 449#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ 450#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ 451#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */ 452#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */ 453#define TWI0_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ 454#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ 455#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ 456#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ 457#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ 458#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ 459 460#define TWI0_REGBASE TWI0_CLKDIV 461 462/* the following are for backwards compatibility */ 463#define TWI0_PRESCALE TWI0_CONTROL 464#define TWI0_INT_SRC TWI0_INT_STAT 465#define TWI0_INT_ENABLE TWI0_INT_MASK 466 467 468/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */ 469 470/* GPIO Port C Register Names */ 471#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */ 472#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */ 473#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */ 474#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */ 475#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */ 476#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */ 477#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */ 478 479/* GPIO Port D Register Names */ 480#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */ 481#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */ 482#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */ 483#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */ 484#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */ 485#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */ 486#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */ 487 488/* GPIO Port E Register Names */ 489#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */ 490#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */ 491#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */ 492#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */ 493#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */ 494#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */ 495#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */ 496 497/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */ 498 499#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */ 500#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */ 501 502/* Alternate deprecated register names (below) provided for backwards code compatibility */ 503#define DMA1_TCPER DMAC1_TC_PER 504#define DMA1_TCCNT DMAC1_TC_CNT 505 506 507/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */ 508#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */ 509#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */ 510#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */ 511#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */ 512#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */ 513#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */ 514#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */ 515#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */ 516#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */ 517#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */ 518#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */ 519#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */ 520#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */ 521 522#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */ 523#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */ 524#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */ 525#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */ 526#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */ 527#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */ 528#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */ 529#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */ 530#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */ 531#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */ 532#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */ 533#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */ 534#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */ 535 536#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */ 537#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */ 538#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */ 539#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */ 540#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */ 541#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */ 542#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */ 543#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */ 544#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */ 545#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */ 546#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */ 547#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */ 548#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */ 549 550#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */ 551#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */ 552#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */ 553#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */ 554#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */ 555#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */ 556#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */ 557#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */ 558#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */ 559#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */ 560#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */ 561#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */ 562#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */ 563 564#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */ 565#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */ 566#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */ 567#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */ 568#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */ 569#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */ 570#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */ 571#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */ 572#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */ 573#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */ 574#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */ 575#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */ 576#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */ 577 578#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */ 579#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */ 580#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */ 581#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */ 582#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */ 583#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */ 584#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */ 585#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */ 586#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */ 587#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */ 588#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */ 589#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */ 590#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */ 591 592#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */ 593#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */ 594#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */ 595#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */ 596#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */ 597#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */ 598#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */ 599#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */ 600#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */ 601#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */ 602#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */ 603#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */ 604#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */ 605 606#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */ 607#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */ 608#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */ 609#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */ 610#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */ 611#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */ 612#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */ 613#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */ 614#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */ 615#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */ 616#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */ 617#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */ 618#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */ 619 620#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */ 621#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */ 622#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */ 623#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */ 624#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */ 625#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */ 626#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */ 627#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */ 628#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */ 629#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */ 630#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */ 631#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */ 632#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */ 633 634#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */ 635#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */ 636#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */ 637#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */ 638#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */ 639#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */ 640#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */ 641#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */ 642#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */ 643#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */ 644#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */ 645#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */ 646#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */ 647 648#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */ 649#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */ 650#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */ 651#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */ 652#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */ 653#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */ 654#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */ 655#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */ 656#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */ 657#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */ 658#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */ 659#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */ 660#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */ 661 662#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */ 663#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */ 664#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */ 665#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */ 666#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */ 667#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */ 668#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */ 669#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */ 670#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */ 671#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */ 672#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */ 673#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */ 674#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */ 675 676#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */ 677#define MDMA1_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */ 678#define MDMA1_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */ 679#define MDMA1_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */ 680#define MDMA1_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */ 681#define MDMA1_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */ 682#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */ 683#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */ 684#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */ 685#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */ 686#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */ 687#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */ 688#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */ 689 690#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */ 691#define MDMA1_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */ 692#define MDMA1_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */ 693#define MDMA1_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */ 694#define MDMA1_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */ 695#define MDMA1_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */ 696#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */ 697#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */ 698#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */ 699#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */ 700#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */ 701#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */ 702#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */ 703 704#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */ 705#define MDMA1_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */ 706#define MDMA1_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */ 707#define MDMA1_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */ 708#define MDMA1_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */ 709#define MDMA1_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */ 710#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */ 711#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */ 712#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */ 713#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */ 714#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */ 715#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */ 716#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */ 717 718#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */ 719#define MDMA1_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */ 720#define MDMA1_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */ 721#define MDMA1_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */ 722#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */ 723#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */ 724#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */ 725#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */ 726#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */ 727#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */ 728#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */ 729#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */ 730#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */ 731 732 733/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */ 734#define UART1_THR 0xFFC02000 /* Transmit Holding register */ 735#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ 736#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ 737#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ 738#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ 739#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ 740#define UART1_LCR 0xFFC0200C /* Line Control Register */ 741#define UART1_MCR 0xFFC02010 /* Modem Control Register */ 742#define UART1_LSR 0xFFC02014 /* Line Status Register */ 743#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ 744#define UART1_GCTL 0xFFC02024 /* Global Control Register */ 745 746 747/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */ 748#define UART2_THR 0xFFC02100 /* Transmit Holding register */ 749#define UART2_RBR 0xFFC02100 /* Receive Buffer register */ 750#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */ 751#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */ 752#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */ 753#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */ 754#define UART2_LCR 0xFFC0210C /* Line Control Register */ 755#define UART2_MCR 0xFFC02110 /* Modem Control Register */ 756#define UART2_LSR 0xFFC02114 /* Line Status Register */ 757#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */ 758#define UART2_GCTL 0xFFC02124 /* Global Control Register */ 759 760 761/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */ 762#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */ 763#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */ 764#define TWI1_SLAVE_CTL 0xFFC02208 /* Slave Mode Control Register */ 765#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */ 766#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */ 767#define TWI1_MASTER_CTL 0xFFC02214 /* Master Mode Control Register */ 768#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */ 769#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */ 770#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */ 771#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */ 772#define TWI1_FIFO_CTL 0xFFC02228 /* FIFO Control Register */ 773#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */ 774#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */ 775#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */ 776#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */ 777#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */ 778#define TWI1_REGBASE TWI1_CLKDIV 779 780 781/* the following are for backwards compatibility */ 782#define TWI1_PRESCALE TWI1_CONTROL 783#define TWI1_INT_SRC TWI1_INT_STAT 784#define TWI1_INT_ENABLE TWI1_INT_MASK 785 786 787/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */ 788#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */ 789#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */ 790#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */ 791#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */ 792#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */ 793#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */ 794#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */ 795#define SPI1_REGBASE SPI1_CTL 796 797/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */ 798#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */ 799#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */ 800#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */ 801#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */ 802#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */ 803#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */ 804#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */ 805#define SPI2_REGBASE SPI2_CTL 806 807/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */ 808#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */ 809#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */ 810#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */ 811#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */ 812#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */ 813#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */ 814#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */ 815#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */ 816#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */ 817#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */ 818#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */ 819#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */ 820#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */ 821#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */ 822#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */ 823#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */ 824#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */ 825#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */ 826#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */ 827#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */ 828#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */ 829#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */ 830 831 832/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */ 833#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */ 834#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */ 835#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */ 836#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */ 837#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */ 838#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */ 839#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */ 840#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */ 841#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */ 842#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */ 843#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */ 844#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */ 845#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */ 846#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */ 847#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */ 848#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */ 849#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */ 850#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */ 851#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */ 852#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */ 853#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */ 854#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */ 855 856 857/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */ 858 859#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */ 860#define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */ 861 862#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */ 863#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */ 864 865#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */ 866#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */ 867 868#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */ 869#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */ 870 871#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */ 872#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */ 873 874#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */ 875#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */ 876 877#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */ 878#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */ 879#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */ 880 881#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */ 882#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */ 883#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */ 884#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */ 885#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */ 886#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */ 887#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */ 888#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */ 889#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */ 890#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */ 891#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */ 892#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */ 893#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */ 894#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */ 895#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */ 896 897#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */ 898#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */ 899#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */ 900#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */ 901#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */ 902#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */ 903#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */ 904#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */ 905 906#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */ 907#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */ 908#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */ 909#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */ 910#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */ 911 912#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */ 913#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */ 914#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */ 915#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */ 916#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */ 917 918#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */ 919#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */ 920#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */ 921#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */ 922#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */ 923 924#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */ 925#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */ 926#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */ 927#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */ 928#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */ 929 930#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */ 931#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */ 932#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */ 933#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */ 934#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */ 935 936#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */ 937#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */ 938#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */ 939#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */ 940#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */ 941 942#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */ 943#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */ 944#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */ 945#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */ 946#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */ 947 948#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */ 949#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */ 950#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */ 951#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */ 952#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */ 953 954#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */ 955#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */ 956#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */ 957#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */ 958#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */ 959 960#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */ 961#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */ 962#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */ 963#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */ 964#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */ 965 966#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */ 967#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */ 968 969#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */ 970#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */ 971#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */ 972#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */ 973 974#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */ 975#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */ 976 977#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */ 978#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */ 979#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */ 980#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */ 981#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */ 982#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */ 983#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */ 984#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */ 985#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */ 986#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */ 987#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */ 988#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */ 989#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */ 990#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */ 991#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */ 992 993#define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */ 994#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */ 995#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */ 996 997 998/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */ 999/* For Mailboxes 0-15 */ 1000#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */ 1001#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */ 1002#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */ 1003#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */ 1004#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */ 1005#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */ 1006#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */ 1007#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */ 1008#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */ 1009#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */ 1010#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */ 1011#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */ 1012#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */ 1013 1014/* For Mailboxes 16-31 */ 1015#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */ 1016#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */ 1017#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */ 1018#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */ 1019#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */ 1020#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */ 1021#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */ 1022#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */ 1023#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */ 1024#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */ 1025#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */ 1026#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */ 1027#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */ 1028 1029#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */ 1030#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */ 1031 1032#define CAN_DEBUG 0xFFC02A88 /* Debug Register */ 1033/* the following is for backwards compatibility */ 1034#define CAN_CNF CAN_DEBUG 1035 1036#define CAN_STATUS 0xFFC02A8C /* Global Status Register */ 1037#define CAN_CEC 0xFFC02A90 /* Error Counter Register */ 1038#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */ 1039#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */ 1040#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ 1041#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ 1042#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ 1043#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ 1044#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ 1045#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ 1046#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */ 1047#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Reload/Capture Register */ 1048#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */ 1049 1050/* Mailbox Acceptance Masks */ 1051#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */ 1052#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */ 1053#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */ 1054#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */ 1055#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */ 1056#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */ 1057#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */ 1058#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */ 1059#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */ 1060#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */ 1061#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */ 1062#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */ 1063#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */ 1064#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */ 1065#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */ 1066#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */ 1067#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */ 1068#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */ 1069#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */ 1070#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */ 1071#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */ 1072#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */ 1073#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */ 1074#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */ 1075#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */ 1076#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */ 1077#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */ 1078#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */ 1079#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */ 1080#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */ 1081#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */ 1082#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */ 1083 1084#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */ 1085#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */ 1086#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */ 1087#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */ 1088#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */ 1089#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */ 1090#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */ 1091#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */ 1092#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */ 1093#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */ 1094#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */ 1095#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */ 1096#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */ 1097#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */ 1098#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */ 1099#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */ 1100#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */ 1101#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */ 1102#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */ 1103#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */ 1104#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */ 1105#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */ 1106#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */ 1107#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */ 1108#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */ 1109#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */ 1110#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */ 1111#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */ 1112#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */ 1113#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */ 1114#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */ 1115#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */ 1116 1117/* CAN Acceptance Mask Macros */ 1118#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8)) 1119#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8)) 1120 1121/* Mailbox Registers */ 1122#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */ 1123#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */ 1124#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */ 1125#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */ 1126#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */ 1127#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */ 1128#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */ 1129#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */ 1130 1131#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */ 1132#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */ 1133#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */ 1134#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */ 1135#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */ 1136#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */ 1137#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */ 1138#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */ 1139 1140#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */ 1141#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */ 1142#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */ 1143#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */ 1144#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */ 1145#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */ 1146#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */ 1147#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */ 1148 1149#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */ 1150#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */ 1151#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */ 1152#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */ 1153#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */ 1154#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */ 1155#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */ 1156#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */ 1157 1158#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */ 1159#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */ 1160#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */ 1161#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */ 1162#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */ 1163#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */ 1164#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */ 1165#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */ 1166 1167#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */ 1168#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */ 1169#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */ 1170#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */ 1171#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */ 1172#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */ 1173#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */ 1174#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */ 1175 1176#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */ 1177#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */ 1178#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */ 1179#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */ 1180#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */ 1181#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */ 1182#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */ 1183#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */ 1184 1185#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */ 1186#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */ 1187#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */ 1188#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */ 1189#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */ 1190#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */ 1191#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */ 1192#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */ 1193 1194#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */ 1195#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */ 1196#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */ 1197#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */ 1198#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */ 1199#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */ 1200#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */ 1201#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */ 1202 1203#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */ 1204#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */ 1205#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */ 1206#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */ 1207#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */ 1208#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */ 1209#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */ 1210#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */ 1211 1212#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */ 1213#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */ 1214#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */ 1215#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */ 1216#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */ 1217#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */ 1218#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */ 1219#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */ 1220 1221#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */ 1222#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */ 1223#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */ 1224#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */ 1225#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */ 1226#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */ 1227#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */ 1228#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */ 1229 1230#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */ 1231#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */ 1232#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */ 1233#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */ 1234#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */ 1235#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */ 1236#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */ 1237#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */ 1238 1239#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */ 1240#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */ 1241#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */ 1242#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */ 1243#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */ 1244#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */ 1245#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */ 1246#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */ 1247 1248#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */ 1249#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */ 1250#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */ 1251#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */ 1252#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */ 1253#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */ 1254#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */ 1255#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */ 1256 1257#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */ 1258#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */ 1259#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */ 1260#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */ 1261#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */ 1262#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */ 1263#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */ 1264#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */ 1265 1266#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */ 1267#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */ 1268#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */ 1269#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */ 1270#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */ 1271#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */ 1272#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */ 1273#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */ 1274 1275#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */ 1276#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */ 1277#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */ 1278#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */ 1279#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */ 1280#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */ 1281#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */ 1282#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */ 1283 1284#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */ 1285#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */ 1286#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */ 1287#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */ 1288#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */ 1289#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */ 1290#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */ 1291#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */ 1292 1293#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */ 1294#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */ 1295#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */ 1296#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */ 1297#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */ 1298#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */ 1299#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */ 1300#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */ 1301 1302#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */ 1303#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */ 1304#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */ 1305#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */ 1306#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */ 1307#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */ 1308#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */ 1309#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */ 1310 1311#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */ 1312#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */ 1313#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */ 1314#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */ 1315#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */ 1316#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */ 1317#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */ 1318#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */ 1319 1320#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */ 1321#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */ 1322#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */ 1323#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */ 1324#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */ 1325#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */ 1326#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */ 1327#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */ 1328 1329#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */ 1330#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */ 1331#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */ 1332#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */ 1333#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */ 1334#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */ 1335#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */ 1336#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */ 1337 1338#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */ 1339#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */ 1340#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */ 1341#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */ 1342#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */ 1343#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */ 1344#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */ 1345#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */ 1346 1347#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */ 1348#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */ 1349#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */ 1350#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */ 1351#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */ 1352#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */ 1353#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */ 1354#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */ 1355 1356#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */ 1357#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */ 1358#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */ 1359#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */ 1360#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */ 1361#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */ 1362#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */ 1363#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */ 1364 1365#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */ 1366#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */ 1367#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */ 1368#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */ 1369#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */ 1370#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */ 1371#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */ 1372#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */ 1373 1374#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */ 1375#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */ 1376#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */ 1377#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */ 1378#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */ 1379#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */ 1380#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */ 1381#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */ 1382 1383#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */ 1384#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */ 1385#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */ 1386#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */ 1387#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */ 1388#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */ 1389#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */ 1390#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */ 1391 1392#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */ 1393#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */ 1394#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */ 1395#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */ 1396#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */ 1397#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */ 1398#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */ 1399#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */ 1400 1401#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */ 1402#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */ 1403#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */ 1404#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */ 1405#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */ 1406#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */ 1407#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */ 1408#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */ 1409 1410/* CAN Mailbox Area Macros */ 1411#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20)) 1412#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20)) 1413#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20)) 1414#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20)) 1415#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20)) 1416#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20)) 1417#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20)) 1418#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20)) 1419 1420 1421/*********************************************************************************** */ 1422/* System MMR Register Bits and Macros */ 1423/******************************************************************************* */ 1424 1425/* SWRST Mask */ 1426#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 1427#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 1428#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ 1429#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ 1430#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 1431 1432/* SYSCR Masks */ 1433#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ 1434#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ 1435 1436 1437/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ 1438 1439/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */ 1440#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */ 1441#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */ 1442#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */ 1443#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */ 1444#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */ 1445#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */ 1446#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */ 1447#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */ 1448#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */ 1449#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */ 1450#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */ 1451#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */ 1452#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */ 1453#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */ 1454#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */ 1455#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */ 1456#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */ 1457#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */ 1458#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */ 1459#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */ 1460#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */ 1461#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */ 1462#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */ 1463#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */ 1464#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */ 1465#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */ 1466#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */ 1467#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */ 1468#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */ 1469#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */ 1470#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */ 1471#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */ 1472 1473/* the following are for backwards compatibility */ 1474#define DMA0_ERR_IRQ DMAC0_ERR_IRQ 1475#define DMA1_ERR_IRQ DMAC1_ERR_IRQ 1476 1477 1478/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */ 1479#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */ 1480#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */ 1481#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */ 1482#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */ 1483#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */ 1484#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */ 1485#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */ 1486#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */ 1487#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */ 1488#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */ 1489#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */ 1490#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */ 1491#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */ 1492#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */ 1493#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */ 1494#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */ 1495#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */ 1496#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */ 1497#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */ 1498#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */ 1499#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */ 1500#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */ 1501 1502/* the following are for backwards compatibility */ 1503#define MDMA0_IRQ MDMA1_0_IRQ 1504#define MDMA1_IRQ MDMA1_1_IRQ 1505 1506#ifdef _MISRA_RULES 1507#define _MF15 0xFu 1508#define _MF7 7u 1509#else 1510#define _MF15 0xF 1511#define _MF7 7 1512#endif /* _MISRA_RULES */ 1513 1514/* SIC_IMASKx Masks */ 1515#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ 1516#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ 1517#ifdef _MISRA_RULES 1518#define SIC_MASK(x) (1 << ((x)&0x1Fu)) /* Mask Peripheral #x interrupt */ 1519#define SIC_UNMASK(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Unmask Peripheral #x interrupt */ 1520#else 1521#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */ 1522#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */ 1523#endif /* _MISRA_RULES */ 1524 1525/* SIC_IWRx Masks */ 1526#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ 1527#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ 1528#ifdef _MISRA_RULES 1529#define IWR_ENABLE(x) (1 << ((x)&0x1Fu)) /* Wakeup Enable Peripheral #x */ 1530#define IWR_DISABLE(x) (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu))) /* Wakeup Disable Peripheral #x */ 1531#else 1532#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1533#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1534#endif /* _MISRA_RULES */ 1535 1536 1537/* ***************************** UART CONTROLLER MASKS ********************** */ 1538/* UARTx_LCR Register */ 1539#ifdef _MISRA_RULES 1540#define WLS(x) (((x)-5u) & 0x03u) /* Word Length Select */ 1541#else 1542#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ 1543#endif /* _MISRA_RULES */ 1544#define STB 0x04 /* Stop Bits */ 1545#define PEN 0x08 /* Parity Enable */ 1546#define EPS 0x10 /* Even Parity Select */ 1547#define STP 0x20 /* Stick Parity */ 1548#define SB 0x40 /* Set Break */ 1549#define DLAB 0x80 /* Divisor Latch Access */ 1550 1551#define DLAB_P 0x07 1552#define SB_P 0x06 1553#define STP_P 0x05 1554#define EPS_P 0x04 1555#define PEN_P 0x03 1556#define STB_P 0x02 1557#define WLS_P1 0x01 1558#define WLS_P0 0x00 1559 1560/* UARTx_MCR Register */ 1561#define LOOP_ENA 0x10 /* Loopback Mode Enable */ 1562#define LOOP_ENA_P 0x04 1563/* Deprecated UARTx_MCR Mask */ 1564 1565/* UARTx_LSR Register */ 1566#define DR 0x01 /* Data Ready */ 1567#define OE 0x02 /* Overrun Error */ 1568#define PE 0x04 /* Parity Error */ 1569#define FE 0x08 /* Framing Error */ 1570#define BI 0x10 /* Break Interrupt */ 1571#define THRE 0x20 /* THR Empty */ 1572#define TEMT 0x40 /* TSR and UART_THR Empty */ 1573 1574#define TEMP_P 0x06 1575#define THRE_P 0x05 1576#define BI_P 0x04 1577#define FE_P 0x03 1578#define PE_P 0x02 1579#define OE_P 0x01 1580#define DR_P 0x00 1581 1582/* UARTx_IER Register */ 1583#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */ 1584#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */ 1585#define ELSI 0x04 /* Enable RX Status Interrupt */ 1586 1587#define ELSI_P 0x02 1588#define ETBEI_P 0x01 1589#define ERBFI_P 0x00 1590 1591/* UARTx_IIR Register */ 1592#define NINT 0x01 1593#define STATUS_P1 0x02 1594#define STATUS_P0 0x01 1595#define NINT_P 0x00 1596 1597/* UARTx_GCTL Register */ 1598#define UCEN 0x01 /* Enable UARTx Clocks */ 1599#define IREN 0x02 /* Enable IrDA Mode */ 1600#define TPOLC 0x04 /* IrDA TX Polarity Change */ 1601#define RPOLC 0x08 /* IrDA RX Polarity Change */ 1602#define FPE 0x10 /* Force Parity Error On Transmit */ 1603#define FFE 0x20 /* Force Framing Error On Transmit */ 1604 1605#define FFE_P 0x05 1606#define FPE_P 0x04 1607#define RPOLC_P 0x03 1608#define TPOLC_P 0x02 1609#define IREN_P 0x01 1610#define UCEN_P 0x00 1611 1612 1613/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 1614/* PPI_CONTROL Masks */ 1615#define PORT_EN 0x0001 /* PPI Port Enable */ 1616#define PORT_DIR 0x0002 /* PPI Port Direction */ 1617#define XFR_TYPE 0x000C /* PPI Transfer Type */ 1618#define PORT_CFG 0x0030 /* PPI Port Configuration */ 1619#define FLD_SEL 0x0040 /* PPI Active Field Select */ 1620#define PACK_EN 0x0080 /* PPI Packing Mode */ 1621/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */ 1622#define SKIP_EN 0x0200 /* PPI Skip Element Enable */ 1623#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */ 1624#define DLENGTH 0x3800 /* PPI Data Length */ 1625#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */ 1626#define DLEN_10 0x0800 /* Data Length = 10 Bits */ 1627#define DLEN_11 0x1000 /* Data Length = 11 Bits */ 1628#define DLEN_12 0x1800 /* Data Length = 12 Bits */ 1629#define DLEN_13 0x2000 /* Data Length = 13 Bits */ 1630#define DLEN_14 0x2800 /* Data Length = 14 Bits */ 1631#define DLEN_15 0x3000 /* Data Length = 15 Bits */ 1632#define DLEN_16 0x3800 /* Data Length = 16 Bits */ 1633#ifdef _MISRA_RULES 1634#define DLEN(x) ((((x)-9u) & 0x07u) << 11) /* PPI Data Length (only works for x=10-->x=16) */ 1635#else 1636#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ 1637#endif /* _MISRA_RULES */ 1638#define POL 0xC000 /* PPI Signal Polarities */ 1639#define POLC 0x4000 /* PPI Clock Polarity */ 1640#define POLS 0x8000 /* PPI Frame Sync Polarity */ 1641 1642 1643/* PPI_STATUS Masks */ 1644#define FLD 0x0400 /* Field Indicator */ 1645#define FT_ERR 0x0800 /* Frame Track Error */ 1646#define OVR 0x1000 /* FIFO Overflow Error */ 1647#define UNDR 0x2000 /* FIFO Underrun Error */ 1648#define ERR_DET 0x4000 /* Error Detected Indicator */ 1649#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */ 1650 1651 1652/* ********** DMA CONTROLLER MASKS ***********************/ 1653 1654/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ 1655 1656#define CTYPE 0x0040 /* DMA Channel Type Indicator */ 1657#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */ 1658#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */ 1659#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */ 1660#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */ 1661#define PCAPWR 0x0400 /* DMA Write Operation Indicator */ 1662#define PCAPRD 0x0800 /* DMA Read Operation Indicator */ 1663#define PMAP 0xF000 /* DMA Peripheral Map Field */ 1664 1665/* PMAP Encodings For DMA Controller 0 */ 1666#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */ 1667#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */ 1668#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */ 1669#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */ 1670#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */ 1671#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */ 1672#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */ 1673#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */ 1674 1675/* PMAP Encodings For DMA Controller 1 */ 1676#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */ 1677#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */ 1678#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */ 1679#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */ 1680#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */ 1681#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */ 1682#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */ 1683#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */ 1684#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */ 1685#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */ 1686 1687 1688/* ************* GENERAL PURPOSE TIMER MASKS ******************** */ 1689/* PWM Timer bit definitions */ 1690/* TIMER_ENABLE Register */ 1691#define TIMEN0 0x0001 /* Enable Timer 0 */ 1692#define TIMEN1 0x0002 /* Enable Timer 1 */ 1693#define TIMEN2 0x0004 /* Enable Timer 2 */ 1694 1695#define TIMEN0_P 0x00 1696#define TIMEN1_P 0x01 1697#define TIMEN2_P 0x02 1698 1699/* TIMER_DISABLE Register */ 1700#define TIMDIS0 0x0001 /* Disable Timer 0 */ 1701#define TIMDIS1 0x0002 /* Disable Timer 1 */ 1702#define TIMDIS2 0x0004 /* Disable Timer 2 */ 1703 1704#define TIMDIS0_P 0x00 1705#define TIMDIS1_P 0x01 1706#define TIMDIS2_P 0x02 1707 1708/* TIMER_STATUS Register */ 1709#define TIMIL0 0x0001 /* Timer 0 Interrupt */ 1710#define TIMIL1 0x0002 /* Timer 1 Interrupt */ 1711#define TIMIL2 0x0004 /* Timer 2 Interrupt */ 1712#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */ 1713#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */ 1714#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */ 1715#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ 1716#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ 1717#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ 1718 1719#define TIMIL0_P 0x00 1720#define TIMIL1_P 0x01 1721#define TIMIL2_P 0x02 1722#define TOVF_ERR0_P 0x04 1723#define TOVF_ERR1_P 0x05 1724#define TOVF_ERR2_P 0x06 1725#define TRUN0_P 0x0C 1726#define TRUN1_P 0x0D 1727#define TRUN2_P 0x0E 1728 1729/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ 1730#define TOVL_ERR0 TOVF_ERR0 1731#define TOVL_ERR1 TOVF_ERR1 1732#define TOVL_ERR2 TOVF_ERR2 1733#define TOVL_ERR0_P TOVF_ERR0_P 1734#define TOVL_ERR1_P TOVF_ERR1_P 1735#define TOVL_ERR2_P TOVF_ERR2_P 1736 1737/* TIMERx_CONFIG Registers */ 1738#define PWM_OUT 0x0001 1739#define WDTH_CAP 0x0002 1740#define EXT_CLK 0x0003 1741#define PULSE_HI 0x0004 1742#define PERIOD_CNT 0x0008 1743#define IRQ_ENA 0x0010 1744#define TIN_SEL 0x0020 1745#define OUT_DIS 0x0040 1746#define CLK_SEL 0x0080 1747#define TOGGLE_HI 0x0100 1748#define EMU_RUN 0x0200 1749#ifdef _MISRA_RULES 1750#define ERR_TYP(x) (((x) & 0x03u) << 14) 1751#else 1752#define ERR_TYP(x) (((x) & 0x03) << 14) 1753#endif /* _MISRA_RULES */ 1754 1755#define TMODE_P0 0x00 1756#define TMODE_P1 0x01 1757#define PULSE_HI_P 0x02 1758#define PERIOD_CNT_P 0x03 1759#define IRQ_ENA_P 0x04 1760#define TIN_SEL_P 0x05 1761#define OUT_DIS_P 0x06 1762#define CLK_SEL_P 0x07 1763#define TOGGLE_HI_P 0x08 1764#define EMU_RUN_P 0x09 1765#define ERR_TYP_P0 0x0E 1766#define ERR_TYP_P1 0x0F 1767 1768 1769/*/ ****************** GENERAL-PURPOSE I/O ********************* */ 1770/* Flag I/O (FIO_) Masks */ 1771#define PF0 0x0001 1772#define PF1 0x0002 1773#define PF2 0x0004 1774#define PF3 0x0008 1775#define PF4 0x0010 1776#define PF5 0x0020 1777#define PF6 0x0040 1778#define PF7 0x0080 1779#define PF8 0x0100 1780#define PF9 0x0200 1781#define PF10 0x0400 1782#define PF11 0x0800 1783#define PF12 0x1000 1784#define PF13 0x2000 1785#define PF14 0x4000 1786#define PF15 0x8000 1787 1788/* PORT F BIT POSITIONS */ 1789#define PF0_P 0x0 1790#define PF1_P 0x1 1791#define PF2_P 0x2 1792#define PF3_P 0x3 1793#define PF4_P 0x4 1794#define PF5_P 0x5 1795#define PF6_P 0x6 1796#define PF7_P 0x7 1797#define PF8_P 0x8 1798#define PF9_P 0x9 1799#define PF10_P 0xA 1800#define PF11_P 0xB 1801#define PF12_P 0xC 1802#define PF13_P 0xD 1803#define PF14_P 0xE 1804#define PF15_P 0xF 1805 1806 1807/******************* GPIO MASKS *********************/ 1808/* Port C Masks */ 1809#define PC0 0x0001 1810#define PC1 0x0002 1811#define PC4 0x0010 1812#define PC5 0x0020 1813#define PC6 0x0040 1814#define PC7 0x0080 1815#define PC8 0x0100 1816#define PC9 0x0200 1817/* Port C Bit Positions */ 1818#define PC0_P 0x0 1819#define PC1_P 0x1 1820#define PC4_P 0x4 1821#define PC5_P 0x5 1822#define PC6_P 0x6 1823#define PC7_P 0x7 1824#define PC8_P 0x8 1825#define PC9_P 0x9 1826 1827/* Port D */ 1828#define PD0 0x0001 1829#define PD1 0x0002 1830#define PD2 0x0004 1831#define PD3 0x0008 1832#define PD4 0x0010 1833#define PD5 0x0020 1834#define PD6 0x0040 1835#define PD7 0x0080 1836#define PD8 0x0100 1837#define PD9 0x0200 1838#define PD10 0x0400 1839#define PD11 0x0800 1840#define PD12 0x1000 1841#define PD13 0x2000 1842#define PD14 0x4000 1843#define PD15 0x8000 1844/* Port D Bit Positions */ 1845#define PD0_P 0x0 1846#define PD1_P 0x1 1847#define PD2_P 0x2 1848#define PD3_P 0x3 1849#define PD4_P 0x4 1850#define PD5_P 0x5 1851#define PD6_P 0x6 1852#define PD7_P 0x7 1853#define PD8_P 0x8 1854#define PD9_P 0x9 1855#define PD10_P 0xA 1856#define PD11_P 0xB 1857#define PD12_P 0xC 1858#define PD13_P 0xD 1859#define PD14_P 0xE 1860#define PD15_P 0xF 1861 1862/* Port E */ 1863#define PE0 0x0001 1864#define PE1 0x0002 1865#define PE2 0x0004 1866#define PE3 0x0008 1867#define PE4 0x0010 1868#define PE5 0x0020 1869#define PE6 0x0040 1870#define PE7 0x0080 1871#define PE8 0x0100 1872#define PE9 0x0200 1873#define PE10 0x0400 1874#define PE11 0x0800 1875#define PE12 0x1000 1876#define PE13 0x2000 1877#define PE14 0x4000 1878#define PE15 0x8000 1879/* Port E Bit Positions */ 1880#define PE0_P 0x0 1881#define PE1_P 0x1 1882#define PE2_P 0x2 1883#define PE3_P 0x3 1884#define PE4_P 0x4 1885#define PE5_P 0x5 1886#define PE6_P 0x6 1887#define PE7_P 0x7 1888#define PE8_P 0x8 1889#define PE9_P 0x9 1890#define PE10_P 0xA 1891#define PE11_P 0xB 1892#define PE12_P 0xC 1893#define PE13_P 0xD 1894#define PE14_P 0xE 1895#define PE15_P 0xF 1896 1897 1898/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */ 1899/* SPIx_CTL Masks */ 1900#define TIMOD 0x0003 /* Transfer Initiate Mode */ 1901#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */ 1902#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */ 1903#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */ 1904#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */ 1905#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */ 1906#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ 1907#define PSSE 0x0010 /* Slave-Select Input Enable */ 1908#define EMISO 0x0020 /* Enable MISO As Output */ 1909#define SIZE 0x0100 /* Size of Words (16/8* Bits) */ 1910#define LSBF 0x0200 /* LSB First */ 1911#define CPHA 0x0400 /* Clock Phase */ 1912#define CPOL 0x0800 /* Clock Polarity */ 1913#define MSTR 0x1000 /* Master/Slave* */ 1914#define WOM 0x2000 /* Write Open Drain Master */ 1915#define SPE 0x4000 /* SPI Enable */ 1916 1917/* SPIx_FLG Masks */ 1918#define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ 1919#define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ 1920#define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ 1921#define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ 1922#define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ 1923#define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ 1924#define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ 1925 1926#define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ 1927#define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ 1928#define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ 1929#define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ 1930#define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ 1931#define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ 1932#define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ 1933 1934/* SPIx_FLG Bit Positions */ 1935#define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */ 1936#define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */ 1937#define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */ 1938#define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */ 1939#define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */ 1940#define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */ 1941#define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */ 1942#define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */ 1943#define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */ 1944#define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */ 1945#define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */ 1946#define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */ 1947#define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */ 1948#define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */ 1949 1950/* SPIx_STAT Masks */ 1951#define SPIF 0x0001 /* Set (=1) when SPI single-word transfer complete */ 1952#define MODF 0x0002 /* Set (=1) in a master device when some other device tries to become master */ 1953#define TXE 0x0004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */ 1954#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */ 1955#define RBSY 0x0010 /* Set (=1) when data is received with RDBR full */ 1956#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ 1957#define TXCOL 0x0040 /* When set (=1), corrupt data may have been transmitted */ 1958 1959/* SPIx_FLG Masks */ 1960#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */ 1961#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */ 1962#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */ 1963#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */ 1964#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */ 1965#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */ 1966#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */ 1967 1968 1969/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 1970/* EBIU_AMGCTL Masks */ 1971#define AMCKEN 0x0001 /* Enable CLKOUT */ 1972#define AMBEN_NONE 0x0000 /* All Banks Disabled */ 1973#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */ 1974#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */ 1975#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ 1976#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ 1977#define CDPRIO 0x0100 /* DMA has priority over core for external accesses */ 1978 1979/* EBIU_AMGCTL Bit Positions */ 1980#define AMCKEN_P 0x0000 /* Enable CLKOUT */ 1981#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ 1982#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ 1983#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ 1984 1985/* EBIU_AMBCTL0 Masks */ 1986#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ 1987#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ 1988#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ 1989#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ 1990#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ 1991#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ 1992#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ 1993#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ 1994#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ 1995#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ 1996#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ 1997#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ 1998#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ 1999#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ 2000#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ 2001#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ 2002#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ 2003#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ 2004#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ 2005#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ 2006#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ 2007#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ 2008#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ 2009#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ 2010#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ 2011#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ 2012#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ 2013#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ 2014#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ 2015#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ 2016#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ 2017#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ 2018#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ 2019#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ 2020#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ 2021#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ 2022#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ 2023#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ 2024#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ 2025#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ 2026#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ 2027#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ 2028#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ 2029#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ 2030#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ 2031#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ 2032#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ 2033#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ 2034#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ 2035#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ 2036#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 2037#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 2038#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 2039#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 2040#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 2041#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 2042#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 2043#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 2044#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ 2045#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ 2046#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ 2047#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ 2048#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ 2049#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ 2050#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ 2051#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ 2052#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ 2053#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ 2054#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ 2055#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ 2056#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ 2057#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ 2058#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ 2059#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ 2060#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ 2061#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ 2062#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ 2063#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ 2064#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ 2065#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ 2066#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ 2067#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ 2068#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ 2069#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ 2070#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ 2071#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ 2072#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ 2073#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ 2074 2075/* EBIU_AMBCTL1 Masks */ 2076#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ 2077#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ 2078#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ 2079#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ 2080#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ 2081#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ 2082#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 2083#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 2084#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 2085#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 2086#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 2087#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 2088#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 2089#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 2090#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ 2091#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ 2092#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ 2093#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ 2094#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ 2095#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ 2096#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ 2097#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ 2098#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ 2099#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ 2100#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ 2101#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ 2102#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ 2103#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ 2104#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ 2105#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ 2106#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ 2107#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ 2108#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ 2109#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ 2110#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ 2111#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ 2112#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ 2113#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ 2114#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ 2115#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ 2116#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ 2117#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ 2118#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ 2119#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ 2120#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ 2121#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ 2122#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ 2123#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ 2124#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ 2125#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ 2126#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 2127#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 2128#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 2129#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 2130#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 2131#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 2132#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 2133#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 2134#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ 2135#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ 2136#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ 2137#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ 2138#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ 2139#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ 2140#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ 2141#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ 2142#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ 2143#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ 2144#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ 2145#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ 2146#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ 2147#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ 2148#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ 2149#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ 2150#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ 2151#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ 2152#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ 2153#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ 2154#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ 2155#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ 2156#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ 2157#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ 2158#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ 2159#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ 2160#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ 2161#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ 2162#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ 2163#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ 2164 2165/* ********************** SDRAM CONTROLLER MASKS *************************** */ 2166/* EBIU_SDGCTL Masks */ 2167#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ 2168#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ 2169#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ 2170#define PFE 0x00000010 /* Enable SDRAM prefetch */ 2171#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ 2172#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ 2173#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ 2174#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ 2175#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ 2176#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ 2177#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ 2178#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ 2179#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ 2180#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ 2181#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ 2182#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ 2183#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ 2184#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ 2185#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ 2186#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ 2187#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ 2188#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ 2189#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ 2190#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ 2191#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ 2192#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ 2193#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ 2194#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ 2195#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ 2196#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ 2197#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ 2198#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ 2199#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ 2200#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ 2201#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ 2202#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ 2203#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ 2204#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ 2205#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ 2206#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ 2207#define PUPSD 0x00200000 /*Power-up start delay */ 2208#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ 2209#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ 2210#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ 2211#define EBUFE 0x02000000 /* Enable external buffering timing */ 2212#define FBBRW 0x04000000 /* Fast back-to-back read write enable */ 2213#define EMREN 0x10000000 /* Extended mode register enable */ 2214#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ 2215#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ 2216 2217/* EBIU_SDBCTL Masks */ 2218#define EBE 0x00000001 /* Enable SDRAM external bank */ 2219#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ 2220#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ 2221#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ 2222#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ 2223#define EBSZ_256 0x00000008 /* SDRAM External Bank Size = 256MB */ 2224#define EBSZ_512 0x0000000A /* SDRAM External Bank Size = 512MB */ 2225#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ 2226#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ 2227#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ 2228#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ 2229 2230/* EBIU_SDSTAT Masks */ 2231#define SDCI 0x00000001 /* SDRAM controller is idle */ 2232#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ 2233#define SDPUA 0x00000004 /* SDRAM power up active */ 2234#define SDRS 0x00000008 /* SDRAM is in reset state */ 2235#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ 2236#define BGSTAT 0x00000020 /* Bus granted */ 2237 2238 2239/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/ 2240/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ 2241#ifdef _MISRA_RULES 2242#define CLKLOW(x) ((x) & 0xFFu) /* Periods Clock Is Held Low */ 2243#define CLKHI(y) (((y)&0xFFu)<<0x8) /* Periods Before New Clock Low */ 2244#else 2245#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ 2246#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ 2247#endif /* _MISRA_RULES */ 2248 2249/* TWIx_PRESCALE Masks */ 2250#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ 2251#define TWI_ENA 0x0080 /* TWI Enable */ 2252#define SCCB 0x0200 /* SCCB Compatibility Enable */ 2253 2254/* TWIx_SLAVE_CTRL Masks */ 2255#define SEN 0x0001 /* Slave Enable */ 2256#define SADD_LEN 0x0002 /* Slave Address Length */ 2257#define STDVAL 0x0004 /* Slave Transmit Data Valid */ 2258#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */ 2259#define GEN 0x0010 /* General Call Adrress Matching Enabled */ 2260 2261/* TWIx_SLAVE_STAT Masks */ 2262#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */ 2263#define GCALL 0x0002 /* General Call Indicator */ 2264 2265/* TWIx_MASTER_CTRL Masks */ 2266#define MEN 0x0001 /* Master Mode Enable */ 2267#define MADD_LEN 0x0002 /* Master Address Length */ 2268#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ 2269#define FAST 0x0008 /* Use Fast Mode Timing Specs */ 2270#define STOP 0x0010 /* Issue Stop Condition */ 2271#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ 2272#define DCNT 0x3FC0 /* Data Bytes To Transfer */ 2273#define SDAOVR 0x4000 /* Serial Data Override */ 2274#define SCLOVR 0x8000 /* Serial Clock Override */ 2275 2276/* TWIx_MASTER_STAT Masks */ 2277#define MPROG 0x0001 /* Master Transfer In Progress */ 2278#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ 2279#define ANAK 0x0004 /* Address Not Acknowledged */ 2280#define DNAK 0x0008 /* Data Not Acknowledged */ 2281#define BUFRDERR 0x0010 /* Buffer Read Error */ 2282#define BUFWRERR 0x0020 /* Buffer Write Error */ 2283#define SDASEN 0x0040 /* Serial Data Sense */ 2284#define SCLSEN 0x0080 /* Serial Clock Sense */ 2285#define BUSBUSY 0x0100 /* Bus Busy Indicator */ 2286 2287/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */ 2288#define SINIT 0x0001 /* Slave Transfer Initiated */ 2289#define SCOMP 0x0002 /* Slave Transfer Complete */ 2290#define SERR 0x0004 /* Slave Transfer Error */ 2291#define SOVF 0x0008 /* Slave Overflow */ 2292#define MCOMP 0x0010 /* Master Transfer Complete */ 2293#define MERR 0x0020 /* Master Transfer Error */ 2294#define XMTSERV 0x0040 /* Transmit FIFO Service */ 2295#define RCVSERV 0x0080 /* Receive FIFO Service */ 2296 2297/* TWIx_FIFO_CTL Masks */ 2298#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ 2299#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ 2300#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ 2301#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ 2302 2303/* TWIx_FIFO_STAT Masks */ 2304#define XMTSTAT 0x0003 /* Transmit FIFO Status */ 2305#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ 2306#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ 2307#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ 2308 2309#define RCVSTAT 0x000C /* Receive FIFO Status */ 2310#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ 2311#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ 2312#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 2313 2314#endif /* _DEF_BF539_H */ 2315