Searched refs:R_IMR_MAILBOX_CPU (Results 1 - 9 of 9) sorted by relevance
| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/sibyte/sb1250/ |
| H A D | smp.c | 43 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
44 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/sibyte/sb1250/ |
| H A D | smp.c | 43 IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU),
44 IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU)
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/src/ |
| H A D | cfe_device_ldr.c | 68 uint64_t *mbox_p = K1_PTR64 (A_IMR_REG(NULL, ISTER(0, R_IMR_MAILBOX_CPU));
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| H A D | dev_sb1250_pcihost.c | 129 uint64_t *mbox_p = K1_PTR64 (A_IMR_REGISTER(0, R_IMR_MAILBOX_CPU));
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| H A D | sb1250_altcpu.S | 244 1: la a0,PHYS_TO_K1(A_IMR_REGISTER(0,R_IMR_MAILBOX_CPU));
674 1: la a0,PHYS_TO_K1(A_IMR_REGISTER(1,R_IMR_MAILBOX_CPU))
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/ |
| H A D | sb1250_regs.h | 704 #define R_IMR_MAILBOX_CPU 0x00c0 macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/sibyte/ |
| H A D | sb1250_regs.h | 726 #define R_IMR_MAILBOX_CPU 0x00c0 macro
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/common/src/ |
| H A D | init_mips.S | 402 li k0,PHYS_TO_K1(A_IMR_REGISTER(0,R_IMR_MAILBOX_CPU))
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| /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/sibyte/ |
| H A D | sb1250_regs.h | 726 #define R_IMR_MAILBOX_CPU 0x00c0 macro
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