1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Register Definitions File: sb1250_regs.h 5 * 6 * This module contains the addresses of the on-chip peripherals 7 * on the SB1250. 8 * 9 * SB1250 specification level: 01/02/2002 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions 27 * as they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. The "Broadcom Corporation" 31 * name may not be used to endorse or promote products derived 32 * from this software without the prior written permission of 33 * Broadcom Corporation. 34 * 35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 39 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 43 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 44 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 45 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 46 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 47 * THE POSSIBILITY OF SUCH DAMAGE. 48 ********************************************************************* */ 49 50 51#ifndef _SB1250_REGS_H 52#define _SB1250_REGS_H 53 54#include "sb1250_defs.h" 55 56 57/* ********************************************************************* 58 * Some general notes: 59 * 60 * For the most part, when there is more than one peripheral 61 * of the same type on the SOC, the constants below will be 62 * offsets from the base of each peripheral. For example, 63 * the MAC registers are described as offsets from the first 64 * MAC register, and there will be a MAC_REGISTER() macro 65 * to calculate the base address of a given MAC. 66 * 67 * The information in this file is based on the SB1250 SOC 68 * manual version 0.2, July 2000. 69 ********************************************************************* */ 70 71 72/* ********************************************************************* 73 * Memory Controller Registers 74 ********************************************************************* */ 75 76#define A_MC_BASE_0 0x0010051000 77#define A_MC_BASE_1 0x0010052000 78#define MC_REGISTER_SPACING 0x1000 79 80#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) 81#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) 82 83#define R_MC_CONFIG 0x0000000100 84#define R_MC_DRAMCMD 0x0000000120 85#define R_MC_DRAMMODE 0x0000000140 86#define R_MC_TIMING1 0x0000000160 87#define R_MC_TIMING2 0x0000000180 88#define R_MC_CS_START 0x00000001A0 89#define R_MC_CS_END 0x00000001C0 90#define R_MC_CS_INTERLEAVE 0x00000001E0 91#define S_MC_CS_STARTEND 16 92 93#define R_MC_CSX_BASE 0x0000000200 94#define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ 95#define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ 96#define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ 97#define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ 98 99#define R_MC_CS0_ROW 0x0000000200 100#define R_MC_CS0_COL 0x0000000220 101#define R_MC_CS0_BA 0x0000000240 102#define R_MC_CS1_ROW 0x0000000260 103#define R_MC_CS1_COL 0x0000000280 104#define R_MC_CS1_BA 0x00000002A0 105#define R_MC_CS2_ROW 0x00000002C0 106#define R_MC_CS2_COL 0x00000002E0 107#define R_MC_CS2_BA 0x0000000300 108#define R_MC_CS3_ROW 0x0000000320 109#define R_MC_CS3_COL 0x0000000340 110#define R_MC_CS3_BA 0x0000000360 111#define R_MC_CS_ATTR 0x0000000380 112#define R_MC_TEST_DATA 0x0000000400 113#define R_MC_TEST_ECC 0x0000000420 114#define R_MC_MCLK_CFG 0x0000000500 115 116/* ********************************************************************* 117 * L2 Cache Control Registers 118 ********************************************************************* */ 119 120#define A_L2_READ_TAG 0x0010040018 121#define A_L2_ECC_TAG 0x0010040038 122#if SIBYTE_HDR_FEATURE(112x, PASS1) 123#define A_L2_READ_MISC 0x0010040058 124#endif /* 112x PASS1 */ 125#define A_L2_WAY_DISABLE 0x0010041000 126#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) 127#define A_L2_MGMT_TAG_BASE 0x00D0000000 128 129#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 130#define A_L2_CACHE_DISABLE 0x0010042000 131#define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) 132#define A_L2_MISC_CONFIG 0x0010043000 133#endif /* 1250 PASS2 || 112x PASS1 */ 134 135/* Backward-compatibility definitions. */ 136#define A_L2_READ_ADDRESS A_L2_READ_TAG 137#define A_L2_EEC_ADDRESS A_L2_ECC_TAG 138 139 140/* ********************************************************************* 141 * PCI Interface Registers 142 ********************************************************************* */ 143 144#define A_PCI_TYPE00_HEADER 0x00DE000000 145#define A_PCI_TYPE01_HEADER 0x00DE000800 146 147 148/* ********************************************************************* 149 * Ethernet DMA and MACs 150 ********************************************************************* */ 151 152#define A_MAC_BASE_0 0x0010064000 153#define A_MAC_BASE_1 0x0010065000 154#if SIBYTE_HDR_FEATURE_CHIP(1250) 155#define A_MAC_BASE_2 0x0010066000 156#endif /* 1250 */ 157 158#define MAC_SPACING 0x1000 159#define MAC_DMA_TXRX_SPACING 0x0400 160#define MAC_DMA_CHANNEL_SPACING 0x0100 161#define DMA_RX 0 162#define DMA_TX 1 163#define MAC_NUM_DMACHAN 2 /* channels per direction */ 164 165#define MAC_NUM_PORTS 3 166 167#define A_MAC_CHANNEL_BASE(macnum) \ 168 (A_MAC_BASE_0 + \ 169 MAC_SPACING*(macnum)) 170 171#define A_MAC_REGISTER(macnum,reg) \ 172 (A_MAC_BASE_0 + \ 173 MAC_SPACING*(macnum) + (reg)) 174 175 176#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ 177 178#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ 179 ((A_MAC_CHANNEL_BASE(macnum)) + \ 180 R_MAC_DMA_CHANNELS + \ 181 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 182 (MAC_DMA_CHANNEL_SPACING*(chan))) 183 184#define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ 185 (R_MAC_DMA_CHANNELS + \ 186 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 187 (MAC_DMA_CHANNEL_SPACING*(chan))) 188 189#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ 190 (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ 191 (reg)) 192 193#define R_MAC_DMA_REGISTER(txrx,chan,reg) \ 194 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ 195 (reg)) 196 197/* 198 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE 199 */ 200 201#define R_MAC_DMA_CONFIG0 0x00000000 202#define R_MAC_DMA_CONFIG1 0x00000008 203#define R_MAC_DMA_DSCR_BASE 0x00000010 204#define R_MAC_DMA_DSCR_CNT 0x00000018 205#define R_MAC_DMA_CUR_DSCRA 0x00000020 206#define R_MAC_DMA_CUR_DSCRB 0x00000028 207#define R_MAC_DMA_CUR_DSCRADDR 0x00000030 208#if SIBYTE_HDR_FEATURE(112x, PASS1) 209#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ 210#endif /* 112x PASS1 */ 211 212/* 213 * RMON Counters 214 */ 215 216#define R_MAC_RMON_TX_BYTES 0x00000000 217#define R_MAC_RMON_COLLISIONS 0x00000008 218#define R_MAC_RMON_LATE_COL 0x00000010 219#define R_MAC_RMON_EX_COL 0x00000018 220#define R_MAC_RMON_FCS_ERROR 0x00000020 221#define R_MAC_RMON_TX_ABORT 0x00000028 222/* Counter #6 (0x30) now reserved */ 223#define R_MAC_RMON_TX_BAD 0x00000038 224#define R_MAC_RMON_TX_GOOD 0x00000040 225#define R_MAC_RMON_TX_RUNT 0x00000048 226#define R_MAC_RMON_TX_OVERSIZE 0x00000050 227#define R_MAC_RMON_RX_BYTES 0x00000080 228#define R_MAC_RMON_RX_MCAST 0x00000088 229#define R_MAC_RMON_RX_BCAST 0x00000090 230#define R_MAC_RMON_RX_BAD 0x00000098 231#define R_MAC_RMON_RX_GOOD 0x000000A0 232#define R_MAC_RMON_RX_RUNT 0x000000A8 233#define R_MAC_RMON_RX_OVERSIZE 0x000000B0 234#define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 235#define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 236#define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 237#define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 238 239/* Updated to spec 0.2 */ 240#define R_MAC_CFG 0x00000100 241#define R_MAC_THRSH_CFG 0x00000108 242#define R_MAC_VLANTAG 0x00000110 243#define R_MAC_FRAMECFG 0x00000118 244#define R_MAC_EOPCNT 0x00000120 245#define R_MAC_FIFO_PTRS 0x00000130 246#define R_MAC_ADFILTER_CFG 0x00000200 247#define R_MAC_ETHERNET_ADDR 0x00000208 248#define R_MAC_PKT_TYPE 0x00000210 249#if SIBYTE_HDR_FEATURE(112x, PASS1) 250#define R_MAC_ADMASK0 0x00000218 251#define R_MAC_ADMASK1 0x00000220 252#endif /* 112x PASS1 */ 253#define R_MAC_HASH_BASE 0x00000240 254#define R_MAC_ADDR_BASE 0x00000280 255#define R_MAC_CHLO0_BASE 0x00000300 256#define R_MAC_CHUP0_BASE 0x00000320 257#define R_MAC_ENABLE 0x00000400 258#define R_MAC_STATUS 0x00000408 259#define R_MAC_INT_MASK 0x00000410 260#define R_MAC_TXD_CTL 0x00000420 261#define R_MAC_MDIO 0x00000428 262#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 263#define R_MAC_STATUS1 0x00000430 264#endif /* 1250 PASS2 || 112x PASS1 */ 265#define R_MAC_DEBUG_STATUS 0x00000448 266 267#define MAC_HASH_COUNT 8 268#define MAC_ADDR_COUNT 8 269#define MAC_CHMAP_COUNT 4 270 271 272/* ********************************************************************* 273 * DUART Registers 274 ********************************************************************* */ 275 276 277#define R_DUART_NUM_PORTS 2 278 279#define A_DUART 0x0010060000 280 281#define A_DUART_REG(r) 282 283#define DUART_CHANREG_SPACING 0x100 284#define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) 285#define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) 286 287#define R_DUART_MODE_REG_1 0x100 288#define R_DUART_MODE_REG_2 0x110 289#define R_DUART_STATUS 0x120 290#define R_DUART_CLK_SEL 0x130 291#define R_DUART_CMD 0x150 292#define R_DUART_RX_HOLD 0x160 293#define R_DUART_TX_HOLD 0x170 294 295#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 296#define R_DUART_FULL_CTL 0x140 297#define R_DUART_OPCR_X 0x180 298#define R_DUART_AUXCTL_X 0x190 299#endif /* 1250 PASS2 || 112x PASS1 */ 300 301 302/* 303 * The IMR and ISR can't be addressed with A_DUART_CHANREG, 304 * so use this macro instead. 305 */ 306 307#define R_DUART_AUX_CTRL 0x310 308#define R_DUART_ISR_A 0x320 309#define R_DUART_IMR_A 0x330 310#define R_DUART_ISR_B 0x340 311#define R_DUART_IMR_B 0x350 312#define R_DUART_OUT_PORT 0x360 313#define R_DUART_OPCR 0x370 314 315#define R_DUART_SET_OPR 0x3B0 316#define R_DUART_CLEAR_OPR 0x3C0 317 318#define DUART_IMRISR_SPACING 0x20 319 320#define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) 321#define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) 322 323#define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) 324#define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) 325 326 327 328 329/* 330 * These constants are the absolute addresses. 331 */ 332 333#define A_DUART_MODE_REG_1_A 0x0010060100 334#define A_DUART_MODE_REG_2_A 0x0010060110 335#define A_DUART_STATUS_A 0x0010060120 336#define A_DUART_CLK_SEL_A 0x0010060130 337#define A_DUART_CMD_A 0x0010060150 338#define A_DUART_RX_HOLD_A 0x0010060160 339#define A_DUART_TX_HOLD_A 0x0010060170 340 341#define A_DUART_MODE_REG_1_B 0x0010060200 342#define A_DUART_MODE_REG_2_B 0x0010060210 343#define A_DUART_STATUS_B 0x0010060220 344#define A_DUART_CLK_SEL_B 0x0010060230 345#define A_DUART_CMD_B 0x0010060250 346#define A_DUART_RX_HOLD_B 0x0010060260 347#define A_DUART_TX_HOLD_B 0x0010060270 348 349#define A_DUART_INPORT_CHNG 0x0010060300 350#define A_DUART_AUX_CTRL 0x0010060310 351#define A_DUART_ISR_A 0x0010060320 352#define A_DUART_IMR_A 0x0010060330 353#define A_DUART_ISR_B 0x0010060340 354#define A_DUART_IMR_B 0x0010060350 355#define A_DUART_OUT_PORT 0x0010060360 356#define A_DUART_OPCR 0x0010060370 357#define A_DUART_IN_PORT 0x0010060380 358#define A_DUART_ISR 0x0010060390 359#define A_DUART_IMR 0x00100603A0 360#define A_DUART_SET_OPR 0x00100603B0 361#define A_DUART_CLEAR_OPR 0x00100603C0 362#define A_DUART_INPORT_CHNG_A 0x00100603D0 363#define A_DUART_INPORT_CHNG_B 0x00100603E0 364 365#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 366#define A_DUART_FULL_CTL_A 0x0010060140 367#define A_DUART_FULL_CTL_B 0x0010060240 368 369#define A_DUART_OPCR_A 0x0010060180 370#define A_DUART_OPCR_B 0x0010060280 371 372#define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 373#endif /* 1250 PASS2 || 112x PASS1 */ 374 375 376/* ********************************************************************* 377 * Synchronous Serial Registers 378 ********************************************************************* */ 379 380 381#define A_SER_BASE_0 0x0010060400 382#define A_SER_BASE_1 0x0010060800 383#define SER_SPACING 0x400 384 385#define SER_DMA_TXRX_SPACING 0x80 386 387#define SER_NUM_PORTS 2 388 389#define A_SER_CHANNEL_BASE(sernum) \ 390 (A_SER_BASE_0 + \ 391 SER_SPACING*(sernum)) 392 393#define A_SER_REGISTER(sernum,reg) \ 394 (A_SER_BASE_0 + \ 395 SER_SPACING*(sernum) + (reg)) 396 397 398#define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ 399 400#define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ 401 ((A_SER_CHANNEL_BASE(sernum)) + \ 402 R_SER_DMA_CHANNELS + \ 403 (SER_DMA_TXRX_SPACING*(txrx))) 404 405#define A_SER_DMA_REGISTER(sernum,txrx,reg) \ 406 (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ 407 (reg)) 408 409 410/* 411 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE 412 */ 413 414#define R_SER_DMA_CONFIG0 0x00000000 415#define R_SER_DMA_CONFIG1 0x00000008 416#define R_SER_DMA_DSCR_BASE 0x00000010 417#define R_SER_DMA_DSCR_CNT 0x00000018 418#define R_SER_DMA_CUR_DSCRA 0x00000020 419#define R_SER_DMA_CUR_DSCRB 0x00000028 420#define R_SER_DMA_CUR_DSCRADDR 0x00000030 421 422#define R_SER_DMA_CONFIG0_RX 0x00000000 423#define R_SER_DMA_CONFIG1_RX 0x00000008 424#define R_SER_DMA_DSCR_BASE_RX 0x00000010 425#define R_SER_DMA_DSCR_COUNT_RX 0x00000018 426#define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 427#define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 428#define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 429 430#define R_SER_DMA_CONFIG0_TX 0x00000080 431#define R_SER_DMA_CONFIG1_TX 0x00000088 432#define R_SER_DMA_DSCR_BASE_TX 0x00000090 433#define R_SER_DMA_DSCR_COUNT_TX 0x00000098 434#define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 435#define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 436#define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 437 438#define R_SER_MODE 0x00000100 439#define R_SER_MINFRM_SZ 0x00000108 440#define R_SER_MAXFRM_SZ 0x00000110 441#define R_SER_ADDR 0x00000118 442#define R_SER_USR0_ADDR 0x00000120 443#define R_SER_USR1_ADDR 0x00000128 444#define R_SER_USR2_ADDR 0x00000130 445#define R_SER_USR3_ADDR 0x00000138 446#define R_SER_CMD 0x00000140 447#define R_SER_TX_RD_THRSH 0x00000160 448#define R_SER_TX_WR_THRSH 0x00000168 449#define R_SER_RX_RD_THRSH 0x00000170 450#define R_SER_LINE_MODE 0x00000178 451#define R_SER_DMA_ENABLE 0x00000180 452#define R_SER_INT_MASK 0x00000190 453#define R_SER_STATUS 0x00000188 454#define R_SER_STATUS_DEBUG 0x000001A8 455#define R_SER_RX_TABLE_BASE 0x00000200 456#define SER_RX_TABLE_COUNT 16 457#define R_SER_TX_TABLE_BASE 0x00000300 458#define SER_TX_TABLE_COUNT 16 459 460/* RMON Counters */ 461#define R_SER_RMON_TX_BYTE_LO 0x000001C0 462#define R_SER_RMON_TX_BYTE_HI 0x000001C8 463#define R_SER_RMON_RX_BYTE_LO 0x000001D0 464#define R_SER_RMON_RX_BYTE_HI 0x000001D8 465#define R_SER_RMON_TX_UNDERRUN 0x000001E0 466#define R_SER_RMON_RX_OVERFLOW 0x000001E8 467#define R_SER_RMON_RX_ERRORS 0x000001F0 468#define R_SER_RMON_RX_BADADDR 0x000001F8 469 470/* ********************************************************************* 471 * Generic Bus Registers 472 ********************************************************************* */ 473 474#define IO_EXT_CFG_COUNT 8 475 476#define A_IO_EXT_BASE 0x0010061000 477#define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) 478 479#define A_IO_EXT_CFG_BASE 0x0010061000 480#define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 481#define A_IO_EXT_START_ADDR_BASE 0x0010061200 482#define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 483#define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 484 485#define IO_EXT_REGISTER_SPACING 8 486#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) 487#define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) 488 489#define R_IO_EXT_CFG 0x0000 490#define R_IO_EXT_MULT_SIZE 0x0100 491#define R_IO_EXT_START_ADDR 0x0200 492#define R_IO_EXT_TIME_CFG0 0x0600 493#define R_IO_EXT_TIME_CFG1 0x0700 494 495 496#define A_IO_INTERRUPT_STATUS 0x0010061A00 497#define A_IO_INTERRUPT_DATA0 0x0010061A10 498#define A_IO_INTERRUPT_DATA1 0x0010061A18 499#define A_IO_INTERRUPT_DATA2 0x0010061A20 500#define A_IO_INTERRUPT_DATA3 0x0010061A28 501#define A_IO_INTERRUPT_ADDR0 0x0010061A30 502#define A_IO_INTERRUPT_ADDR1 0x0010061A40 503#define A_IO_INTERRUPT_PARITY 0x0010061A50 504#define A_IO_PCMCIA_CFG 0x0010061A60 505#define A_IO_PCMCIA_STATUS 0x0010061A70 506#define A_IO_DRIVE_0 0x0010061300 507#define A_IO_DRIVE_1 0x0010061308 508#define A_IO_DRIVE_2 0x0010061310 509#define A_IO_DRIVE_3 0x0010061318 510#define A_IO_DRIVE_BASE A_IO_DRIVE_0 511#define IO_DRIVE_REGISTER_SPACING 8 512#define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) 513#define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) 514 515#define R_IO_INTERRUPT_STATUS 0x0A00 516#define R_IO_INTERRUPT_DATA0 0x0A10 517#define R_IO_INTERRUPT_DATA1 0x0A18 518#define R_IO_INTERRUPT_DATA2 0x0A20 519#define R_IO_INTERRUPT_DATA3 0x0A28 520#define R_IO_INTERRUPT_ADDR0 0x0A30 521#define R_IO_INTERRUPT_ADDR1 0x0A40 522#define R_IO_INTERRUPT_PARITY 0x0A50 523#define R_IO_PCMCIA_CFG 0x0A60 524#define R_IO_PCMCIA_STATUS 0x0A70 525 526/* ********************************************************************* 527 * GPIO Registers 528 ********************************************************************* */ 529 530#define A_GPIO_CLR_EDGE 0x0010061A80 531#define A_GPIO_INT_TYPE 0x0010061A88 532#define A_GPIO_INPUT_INVERT 0x0010061A90 533#define A_GPIO_GLITCH 0x0010061A98 534#define A_GPIO_READ 0x0010061AA0 535#define A_GPIO_DIRECTION 0x0010061AA8 536#define A_GPIO_PIN_CLR 0x0010061AB0 537#define A_GPIO_PIN_SET 0x0010061AB8 538 539#define A_GPIO_BASE 0x0010061A80 540 541#define R_GPIO_CLR_EDGE 0x00 542#define R_GPIO_INT_TYPE 0x08 543#define R_GPIO_INPUT_INVERT 0x10 544#define R_GPIO_GLITCH 0x18 545#define R_GPIO_READ 0x20 546#define R_GPIO_DIRECTION 0x28 547#define R_GPIO_PIN_CLR 0x30 548#define R_GPIO_PIN_SET 0x38 549 550/* ********************************************************************* 551 * SMBus Registers 552 ********************************************************************* */ 553 554#define A_SMB_XTRA_0 0x0010060000 555#define A_SMB_XTRA_1 0x0010060008 556#define A_SMB_FREQ_0 0x0010060010 557#define A_SMB_FREQ_1 0x0010060018 558#define A_SMB_STATUS_0 0x0010060020 559#define A_SMB_STATUS_1 0x0010060028 560#define A_SMB_CMD_0 0x0010060030 561#define A_SMB_CMD_1 0x0010060038 562#define A_SMB_START_0 0x0010060040 563#define A_SMB_START_1 0x0010060048 564#define A_SMB_DATA_0 0x0010060050 565#define A_SMB_DATA_1 0x0010060058 566#define A_SMB_CONTROL_0 0x0010060060 567#define A_SMB_CONTROL_1 0x0010060068 568#define A_SMB_PEC_0 0x0010060070 569#define A_SMB_PEC_1 0x0010060078 570 571#define A_SMB_0 0x0010060000 572#define A_SMB_1 0x0010060008 573#define SMB_REGISTER_SPACING 0x8 574#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) 575#define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) 576 577#define R_SMB_XTRA 0x0000000000 578#define R_SMB_FREQ 0x0000000010 579#define R_SMB_STATUS 0x0000000020 580#define R_SMB_CMD 0x0000000030 581#define R_SMB_START 0x0000000040 582#define R_SMB_DATA 0x0000000050 583#define R_SMB_CONTROL 0x0000000060 584#define R_SMB_PEC 0x0000000070 585 586/* ********************************************************************* 587 * Timer Registers 588 ********************************************************************* */ 589 590/* 591 * Watchdog timers 592 */ 593 594#define A_SCD_WDOG_0 0x0010020050 595#define A_SCD_WDOG_1 0x0010020150 596#define SCD_WDOG_SPACING 0x100 597#define SCD_NUM_WDOGS 2 598#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) 599#define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) 600 601#define R_SCD_WDOG_INIT 0x0000000000 602#define R_SCD_WDOG_CNT 0x0000000008 603#define R_SCD_WDOG_CFG 0x0000000010 604 605#define A_SCD_WDOG_INIT_0 0x0010020050 606#define A_SCD_WDOG_CNT_0 0x0010020058 607#define A_SCD_WDOG_CFG_0 0x0010020060 608 609#define A_SCD_WDOG_INIT_1 0x0010020150 610#define A_SCD_WDOG_CNT_1 0x0010020158 611#define A_SCD_WDOG_CFG_1 0x0010020160 612 613/* 614 * Generic timers 615 */ 616 617#define A_SCD_TIMER_0 0x0010020070 618#define A_SCD_TIMER_1 0x0010020078 619#define A_SCD_TIMER_2 0x0010020170 620#define A_SCD_TIMER_3 0x0010020178 621#define SCD_NUM_TIMERS 4 622#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) 623#define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) 624 625#define R_SCD_TIMER_INIT 0x0000000000 626#define R_SCD_TIMER_CNT 0x0000000010 627#define R_SCD_TIMER_CFG 0x0000000020 628 629#define A_SCD_TIMER_INIT_0 0x0010020070 630#define A_SCD_TIMER_CNT_0 0x0010020080 631#define A_SCD_TIMER_CFG_0 0x0010020090 632 633#define A_SCD_TIMER_INIT_1 0x0010020078 634#define A_SCD_TIMER_CNT_1 0x0010020088 635#define A_SCD_TIMER_CFG_1 0x0010020098 636 637#define A_SCD_TIMER_INIT_2 0x0010020170 638#define A_SCD_TIMER_CNT_2 0x0010020180 639#define A_SCD_TIMER_CFG_2 0x0010020190 640 641#define A_SCD_TIMER_INIT_3 0x0010020178 642#define A_SCD_TIMER_CNT_3 0x0010020188 643#define A_SCD_TIMER_CFG_3 0x0010020198 644 645#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 646#define A_SCD_SCRATCH 0x0010020C10 647 648#define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 649#define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 650#define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 651#endif /* 1250 PASS2 || 112x PASS1 */ 652 653 654/* ********************************************************************* 655 * System Control Registers 656 ********************************************************************* */ 657 658#define A_SCD_SYSTEM_REVISION 0x0010020000 659#define A_SCD_SYSTEM_CFG 0x0010020008 660#define A_SCD_SYSTEM_MANUF 0x0010038000 661 662/* ********************************************************************* 663 * System Address Trap Registers 664 ********************************************************************* */ 665 666#define A_ADDR_TRAP_INDEX 0x00100200B0 667#define A_ADDR_TRAP_REG 0x00100200B8 668#define A_ADDR_TRAP_UP_0 0x0010020400 669#define A_ADDR_TRAP_UP_1 0x0010020408 670#define A_ADDR_TRAP_UP_2 0x0010020410 671#define A_ADDR_TRAP_UP_3 0x0010020418 672#define A_ADDR_TRAP_DOWN_0 0x0010020420 673#define A_ADDR_TRAP_DOWN_1 0x0010020428 674#define A_ADDR_TRAP_DOWN_2 0x0010020430 675#define A_ADDR_TRAP_DOWN_3 0x0010020438 676#define A_ADDR_TRAP_CFG_0 0x0010020440 677#define A_ADDR_TRAP_CFG_1 0x0010020448 678#define A_ADDR_TRAP_CFG_2 0x0010020450 679#define A_ADDR_TRAP_CFG_3 0x0010020458 680#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 681#define A_ADDR_TRAP_REG_DEBUG 0x0010020460 682#endif /* 1250 PASS2 || 112x PASS1 */ 683 684 685/* ********************************************************************* 686 * System Interrupt Mapper Registers 687 ********************************************************************* */ 688 689#define A_IMR_CPU0_BASE 0x0010020000 690#define A_IMR_CPU1_BASE 0x0010022000 691#define IMR_REGISTER_SPACING 0x2000 692#define IMR_REGISTER_SPACING_SHIFT 13 693 694#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) 695#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) 696 697#define R_IMR_INTERRUPT_DIAG 0x0010 698#define R_IMR_INTERRUPT_MASK 0x0028 699#define R_IMR_INTERRUPT_TRACE 0x0038 700#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 701#define R_IMR_LDT_INTERRUPT_SET 0x0048 702#define R_IMR_LDT_INTERRUPT 0x0018 703#define R_IMR_LDT_INTERRUPT_CLR 0x0020 704#define R_IMR_MAILBOX_CPU 0x00c0 705#define R_IMR_ALIAS_MAILBOX_CPU 0x1000 706#define R_IMR_MAILBOX_SET_CPU 0x00C8 707#define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 708#define R_IMR_MAILBOX_CLR_CPU 0x00D0 709#define R_IMR_INTERRUPT_STATUS_BASE 0x0100 710#define R_IMR_INTERRUPT_STATUS_COUNT 7 711#define R_IMR_INTERRUPT_MAP_BASE 0x0200 712#define R_IMR_INTERRUPT_MAP_COUNT 64 713 714/* ********************************************************************* 715 * System Performance Counter Registers 716 ********************************************************************* */ 717 718#define A_SCD_PERF_CNT_CFG 0x00100204C0 719#define A_SCD_PERF_CNT_0 0x00100204D0 720#define A_SCD_PERF_CNT_1 0x00100204D8 721#define A_SCD_PERF_CNT_2 0x00100204E0 722#define A_SCD_PERF_CNT_3 0x00100204E8 723 724/* ********************************************************************* 725 * System Bus Watcher Registers 726 ********************************************************************* */ 727 728#define A_SCD_BUS_ERR_STATUS 0x0010020880 729#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 730#define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 731#endif /* 1250 PASS2 || 112x PASS1 */ 732#define A_BUS_ERR_DATA_0 0x00100208A0 733#define A_BUS_ERR_DATA_1 0x00100208A8 734#define A_BUS_ERR_DATA_2 0x00100208B0 735#define A_BUS_ERR_DATA_3 0x00100208B8 736#define A_BUS_L2_ERRORS 0x00100208C0 737#define A_BUS_MEM_IO_ERRORS 0x00100208C8 738 739/* ********************************************************************* 740 * System Debug Controller Registers 741 ********************************************************************* */ 742 743#define A_SCD_JTAG_BASE 0x0010000000 744 745/* ********************************************************************* 746 * System Trace Buffer Registers 747 ********************************************************************* */ 748 749#define A_SCD_TRACE_CFG 0x0010020A00 750#define A_SCD_TRACE_READ 0x0010020A08 751#define A_SCD_TRACE_EVENT_0 0x0010020A20 752#define A_SCD_TRACE_EVENT_1 0x0010020A28 753#define A_SCD_TRACE_EVENT_2 0x0010020A30 754#define A_SCD_TRACE_EVENT_3 0x0010020A38 755#define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 756#define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 757#define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 758#define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 759#define A_SCD_TRACE_EVENT_4 0x0010020A60 760#define A_SCD_TRACE_EVENT_5 0x0010020A68 761#define A_SCD_TRACE_EVENT_6 0x0010020A70 762#define A_SCD_TRACE_EVENT_7 0x0010020A78 763#define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 764#define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 765#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 766#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 767 768/* ********************************************************************* 769 * System Generic DMA Registers 770 ********************************************************************* */ 771 772#define A_DM_0 0x0010020B00 773#define A_DM_1 0x0010020B20 774#define A_DM_2 0x0010020B40 775#define A_DM_3 0x0010020B60 776#define DM_REGISTER_SPACING 0x20 777#define DM_NUM_CHANNELS 4 778#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) 779#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) 780 781#define R_DM_DSCR_BASE 0x0000000000 782#define R_DM_DSCR_COUNT 0x0000000008 783#define R_DM_CUR_DSCR_ADDR 0x0000000010 784#define R_DM_DSCR_BASE_DEBUG 0x0000000018 785 786#if SIBYTE_HDR_FEATURE(112x, PASS1) 787#define A_DM_PARTIAL_0 0x0010020ba0 788#define A_DM_PARTIAL_1 0x0010020ba8 789#define A_DM_PARTIAL_2 0x0010020bb0 790#define A_DM_PARTIAL_3 0x0010020bb8 791#define DM_PARTIAL_REGISTER_SPACING 0x8 792#define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING)) 793#endif /* 112x PASS1 */ 794 795#if SIBYTE_HDR_FEATURE(112x, PASS1) 796#define A_DM_CRC_0 0x0010020b80 797#define A_DM_CRC_1 0x0010020b90 798#define DM_CRC_REGISTER_SPACING 0x10 799#define DM_CRC_NUM_CHANNELS 2 800#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) 801#define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg)) 802 803#define R_CRC_DEF_0 0x00 804#define R_CTCP_DEF_0 0x08 805#endif /* 112x PASS1 */ 806 807/* ********************************************************************* 808 * Physical Address Map 809 ********************************************************************* */ 810 811#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) 812#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) 813#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) 814#define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) 815#define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) 816#define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) 817#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) 818#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) 819#define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) 820#define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) 821#define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) 822#define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) 823#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) 824#define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) 825#define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) 826#define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) 827#define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) 828#define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) 829#define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) 830#define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) 831#define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) 832#define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) 833#define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) 834#define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) 835#define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) 836 837#define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) 838#define PHYS_L2CACHE_NUM_WAYS 4 839#define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) 840#define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) 841#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) 842#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) 843#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) 844 845 846#endif 847