1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Register Definitions File: sb1250_regs.h 5 * 6 * This module contains the addresses of the on-chip peripherals 7 * on the SB1250. 8 * 9 * SB1250 specification level: 01/02/2002 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 ********************************************************************* */ 31 32 33#ifndef _SB1250_REGS_H 34#define _SB1250_REGS_H 35 36#include "sb1250_defs.h" 37 38 39/* ********************************************************************* 40 * Some general notes: 41 * 42 * For the most part, when there is more than one peripheral 43 * of the same type on the SOC, the constants below will be 44 * offsets from the base of each peripheral. For example, 45 * the MAC registers are described as offsets from the first 46 * MAC register, and there will be a MAC_REGISTER() macro 47 * to calculate the base address of a given MAC. 48 * 49 * The information in this file is based on the SB1250 SOC 50 * manual version 0.2, July 2000. 51 ********************************************************************* */ 52 53 54/* ********************************************************************* 55 * Memory Controller Registers 56 ********************************************************************* */ 57 58 59#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ 60#define A_MC_BASE_0 0x0010051000 61#define A_MC_BASE_1 0x0010052000 62#define MC_REGISTER_SPACING 0x1000 63 64#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) 65#define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg)) 66 67#define R_MC_CONFIG 0x0000000100 68#define R_MC_DRAMCMD 0x0000000120 69#define R_MC_DRAMMODE 0x0000000140 70#define R_MC_TIMING1 0x0000000160 71#define R_MC_TIMING2 0x0000000180 72#define R_MC_CS_START 0x00000001A0 73#define R_MC_CS_END 0x00000001C0 74#define R_MC_CS_INTERLEAVE 0x00000001E0 75#define S_MC_CS_STARTEND 16 76 77#define R_MC_CSX_BASE 0x0000000200 78#define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ 79#define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ 80#define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ 81#define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ 82 83#define R_MC_CS0_ROW 0x0000000200 84#define R_MC_CS0_COL 0x0000000220 85#define R_MC_CS0_BA 0x0000000240 86#define R_MC_CS1_ROW 0x0000000260 87#define R_MC_CS1_COL 0x0000000280 88#define R_MC_CS1_BA 0x00000002A0 89#define R_MC_CS2_ROW 0x00000002C0 90#define R_MC_CS2_COL 0x00000002E0 91#define R_MC_CS2_BA 0x0000000300 92#define R_MC_CS3_ROW 0x0000000320 93#define R_MC_CS3_COL 0x0000000340 94#define R_MC_CS3_BA 0x0000000360 95#define R_MC_CS_ATTR 0x0000000380 96#define R_MC_TEST_DATA 0x0000000400 97#define R_MC_TEST_ECC 0x0000000420 98#define R_MC_MCLK_CFG 0x0000000500 99 100#endif /* 1250 & 112x */ 101 102/* ********************************************************************* 103 * L2 Cache Control Registers 104 ********************************************************************* */ 105 106#if SIBYTE_HDR_FEATURE_1250_112x /* This L2C only on 1250/112x */ 107 108#define A_L2_READ_TAG 0x0010040018 109#define A_L2_ECC_TAG 0x0010040038 110#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 111#define A_L2_READ_MISC 0x0010040058 112#endif /* 1250 PASS3 || 112x PASS1 */ 113#define A_L2_WAY_DISABLE 0x0010041000 114#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) 115#define A_L2_MGMT_TAG_BASE 0x00D0000000 116 117#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 118#define A_L2_CACHE_DISABLE 0x0010042000 119#define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) 120#define A_L2_MISC_CONFIG 0x0010043000 121#endif /* 1250 PASS2 || 112x PASS1 */ 122 123/* Backward-compatibility definitions. */ 124#define A_L2_READ_ADDRESS A_L2_READ_TAG 125#define A_L2_EEC_ADDRESS A_L2_ECC_TAG 126 127#endif 128 129 130/* ********************************************************************* 131 * PCI Interface Registers 132 ********************************************************************* */ 133 134#if SIBYTE_HDR_FEATURE_1250_112x /* This PCI/HT only on 1250/112x */ 135#define A_PCI_TYPE00_HEADER 0x00DE000000 136#define A_PCI_TYPE01_HEADER 0x00DE000800 137#endif 138 139 140/* ********************************************************************* 141 * Ethernet DMA and MACs 142 ********************************************************************* */ 143 144#define A_MAC_BASE_0 0x0010064000 145#define A_MAC_BASE_1 0x0010065000 146#if SIBYTE_HDR_FEATURE_CHIP(1250) 147#define A_MAC_BASE_2 0x0010066000 148#endif /* 1250 */ 149 150#define MAC_SPACING 0x1000 151#define MAC_DMA_TXRX_SPACING 0x0400 152#define MAC_DMA_CHANNEL_SPACING 0x0100 153#define DMA_RX 0 154#define DMA_TX 1 155#define MAC_NUM_DMACHAN 2 /* channels per direction */ 156 157#define MAC_NUM_PORTS 3 158 159#define A_MAC_CHANNEL_BASE(macnum) \ 160 (A_MAC_BASE_0 + \ 161 MAC_SPACING*(macnum)) 162 163#define A_MAC_REGISTER(macnum,reg) \ 164 (A_MAC_BASE_0 + \ 165 MAC_SPACING*(macnum) + (reg)) 166 167 168#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ 169 170#define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) \ 171 ((A_MAC_CHANNEL_BASE(macnum)) + \ 172 R_MAC_DMA_CHANNELS + \ 173 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 174 (MAC_DMA_CHANNEL_SPACING*(chan))) 175 176#define R_MAC_DMA_CHANNEL_BASE(txrx, chan) \ 177 (R_MAC_DMA_CHANNELS + \ 178 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 179 (MAC_DMA_CHANNEL_SPACING*(chan))) 180 181#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \ 182 (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \ 183 (reg)) 184 185#define R_MAC_DMA_REGISTER(txrx, chan, reg) \ 186 (R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \ 187 (reg)) 188 189/* 190 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE 191 */ 192 193#define R_MAC_DMA_CONFIG0 0x00000000 194#define R_MAC_DMA_CONFIG1 0x00000008 195#define R_MAC_DMA_DSCR_BASE 0x00000010 196#define R_MAC_DMA_DSCR_CNT 0x00000018 197#define R_MAC_DMA_CUR_DSCRA 0x00000020 198#define R_MAC_DMA_CUR_DSCRB 0x00000028 199#define R_MAC_DMA_CUR_DSCRADDR 0x00000030 200#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 201#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ 202#endif /* 1250 PASS3 || 112x PASS1 */ 203 204/* 205 * RMON Counters 206 */ 207 208#define R_MAC_RMON_TX_BYTES 0x00000000 209#define R_MAC_RMON_COLLISIONS 0x00000008 210#define R_MAC_RMON_LATE_COL 0x00000010 211#define R_MAC_RMON_EX_COL 0x00000018 212#define R_MAC_RMON_FCS_ERROR 0x00000020 213#define R_MAC_RMON_TX_ABORT 0x00000028 214/* Counter #6 (0x30) now reserved */ 215#define R_MAC_RMON_TX_BAD 0x00000038 216#define R_MAC_RMON_TX_GOOD 0x00000040 217#define R_MAC_RMON_TX_RUNT 0x00000048 218#define R_MAC_RMON_TX_OVERSIZE 0x00000050 219#define R_MAC_RMON_RX_BYTES 0x00000080 220#define R_MAC_RMON_RX_MCAST 0x00000088 221#define R_MAC_RMON_RX_BCAST 0x00000090 222#define R_MAC_RMON_RX_BAD 0x00000098 223#define R_MAC_RMON_RX_GOOD 0x000000A0 224#define R_MAC_RMON_RX_RUNT 0x000000A8 225#define R_MAC_RMON_RX_OVERSIZE 0x000000B0 226#define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 227#define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 228#define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 229#define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 230 231/* Updated to spec 0.2 */ 232#define R_MAC_CFG 0x00000100 233#define R_MAC_THRSH_CFG 0x00000108 234#define R_MAC_VLANTAG 0x00000110 235#define R_MAC_FRAMECFG 0x00000118 236#define R_MAC_EOPCNT 0x00000120 237#define R_MAC_FIFO_PTRS 0x00000128 238#define R_MAC_ADFILTER_CFG 0x00000200 239#define R_MAC_ETHERNET_ADDR 0x00000208 240#define R_MAC_PKT_TYPE 0x00000210 241#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 242 SIBYTE_HDR_FEATURE_CHIP(1480) 243#define R_MAC_ADMASK0 0x00000218 244#define R_MAC_ADMASK1 0x00000220 245#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 246#define R_MAC_HASH_BASE 0x00000240 247#define R_MAC_ADDR_BASE 0x00000280 248#define R_MAC_CHLO0_BASE 0x00000300 249#define R_MAC_CHUP0_BASE 0x00000320 250#define R_MAC_ENABLE 0x00000400 251#define R_MAC_STATUS 0x00000408 252#define R_MAC_INT_MASK 0x00000410 253#define R_MAC_TXD_CTL 0x00000420 254#define R_MAC_MDIO 0x00000428 255#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 256 SIBYTE_HDR_FEATURE_CHIP(1480) 257#define R_MAC_STATUS1 0x00000430 258#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 259#define R_MAC_DEBUG_STATUS 0x00000448 260 261#define MAC_HASH_COUNT 8 262#define MAC_ADDR_COUNT 8 263#define MAC_CHMAP_COUNT 4 264 265 266/* ********************************************************************* 267 * DUART Registers 268 ********************************************************************* */ 269 270 271#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ 272#define R_DUART_NUM_PORTS 2 273 274#define A_DUART 0x0010060000 275 276#define DUART_CHANREG_SPACING 0x100 277 278#define A_DUART_CHANREG(chan, reg) \ 279 (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg)) 280#endif /* 1250 & 112x */ 281 282#define R_DUART_MODE_REG_1 0x000 283#define R_DUART_MODE_REG_2 0x010 284#define R_DUART_STATUS 0x020 285#define R_DUART_CLK_SEL 0x030 286#define R_DUART_CMD 0x050 287#define R_DUART_RX_HOLD 0x060 288#define R_DUART_TX_HOLD 0x070 289 290#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 291 SIBYTE_HDR_FEATURE_CHIP(1480) 292#define R_DUART_FULL_CTL 0x040 293#define R_DUART_OPCR_X 0x080 294#define R_DUART_AUXCTL_X 0x090 295#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 296 297 298/* 299 * The IMR and ISR can't be addressed with A_DUART_CHANREG, 300 * so use these macros instead. 301 */ 302 303#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ 304#define DUART_IMRISR_SPACING 0x20 305#define DUART_INCHNG_SPACING 0x10 306 307#define A_DUART_CTRLREG(reg) \ 308 (A_DUART + DUART_CHANREG_SPACING * 3 + (reg)) 309 310#define R_DUART_IMRREG(chan) \ 311 (R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING) 312#define R_DUART_ISRREG(chan) \ 313 (R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING) 314#define R_DUART_INCHREG(chan) \ 315 (R_DUART_IN_CHNG_A + (chan) * DUART_INCHNG_SPACING) 316 317#define A_DUART_IMRREG(chan) A_DUART_CTRLREG(R_DUART_IMRREG(chan)) 318#define A_DUART_ISRREG(chan) A_DUART_CTRLREG(R_DUART_ISRREG(chan)) 319#define A_DUART_INCHREG(chan) A_DUART_CTRLREG(R_DUART_INCHREG(chan)) 320#endif /* 1250 & 112x */ 321 322#define R_DUART_AUX_CTRL 0x010 323#define R_DUART_ISR_A 0x020 324#define R_DUART_IMR_A 0x030 325#define R_DUART_ISR_B 0x040 326#define R_DUART_IMR_B 0x050 327#define R_DUART_OUT_PORT 0x060 328#define R_DUART_OPCR 0x070 329#define R_DUART_IN_PORT 0x080 330 331#define R_DUART_SET_OPR 0x0B0 332#define R_DUART_CLEAR_OPR 0x0C0 333#define R_DUART_IN_CHNG_A 0x0D0 334#define R_DUART_IN_CHNG_B 0x0E0 335 336 337/* 338 * These constants are the absolute addresses. 339 */ 340 341#define A_DUART_MODE_REG_1_A 0x0010060100 342#define A_DUART_MODE_REG_2_A 0x0010060110 343#define A_DUART_STATUS_A 0x0010060120 344#define A_DUART_CLK_SEL_A 0x0010060130 345#define A_DUART_CMD_A 0x0010060150 346#define A_DUART_RX_HOLD_A 0x0010060160 347#define A_DUART_TX_HOLD_A 0x0010060170 348 349#define A_DUART_MODE_REG_1_B 0x0010060200 350#define A_DUART_MODE_REG_2_B 0x0010060210 351#define A_DUART_STATUS_B 0x0010060220 352#define A_DUART_CLK_SEL_B 0x0010060230 353#define A_DUART_CMD_B 0x0010060250 354#define A_DUART_RX_HOLD_B 0x0010060260 355#define A_DUART_TX_HOLD_B 0x0010060270 356 357#define A_DUART_INPORT_CHNG 0x0010060300 358#define A_DUART_AUX_CTRL 0x0010060310 359#define A_DUART_ISR_A 0x0010060320 360#define A_DUART_IMR_A 0x0010060330 361#define A_DUART_ISR_B 0x0010060340 362#define A_DUART_IMR_B 0x0010060350 363#define A_DUART_OUT_PORT 0x0010060360 364#define A_DUART_OPCR 0x0010060370 365#define A_DUART_IN_PORT 0x0010060380 366#define A_DUART_ISR 0x0010060390 367#define A_DUART_IMR 0x00100603A0 368#define A_DUART_SET_OPR 0x00100603B0 369#define A_DUART_CLEAR_OPR 0x00100603C0 370#define A_DUART_INPORT_CHNG_A 0x00100603D0 371#define A_DUART_INPORT_CHNG_B 0x00100603E0 372 373#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 374#define A_DUART_FULL_CTL_A 0x0010060140 375#define A_DUART_FULL_CTL_B 0x0010060240 376 377#define A_DUART_OPCR_A 0x0010060180 378#define A_DUART_OPCR_B 0x0010060280 379 380#define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 381#endif /* 1250 PASS2 || 112x PASS1 */ 382 383 384/* ********************************************************************* 385 * Synchronous Serial Registers 386 ********************************************************************* */ 387 388 389#if SIBYTE_HDR_FEATURE_1250_112x /* sync serial only on 1250/112x */ 390 391#define A_SER_BASE_0 0x0010060400 392#define A_SER_BASE_1 0x0010060800 393#define SER_SPACING 0x400 394 395#define SER_DMA_TXRX_SPACING 0x80 396 397#define SER_NUM_PORTS 2 398 399#define A_SER_CHANNEL_BASE(sernum) \ 400 (A_SER_BASE_0 + \ 401 SER_SPACING*(sernum)) 402 403#define A_SER_REGISTER(sernum,reg) \ 404 (A_SER_BASE_0 + \ 405 SER_SPACING*(sernum) + (reg)) 406 407 408#define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ 409 410#define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ 411 ((A_SER_CHANNEL_BASE(sernum)) + \ 412 R_SER_DMA_CHANNELS + \ 413 (SER_DMA_TXRX_SPACING*(txrx))) 414 415#define A_SER_DMA_REGISTER(sernum, txrx, reg) \ 416 (A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \ 417 (reg)) 418 419 420/* 421 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE 422 */ 423 424#define R_SER_DMA_CONFIG0 0x00000000 425#define R_SER_DMA_CONFIG1 0x00000008 426#define R_SER_DMA_DSCR_BASE 0x00000010 427#define R_SER_DMA_DSCR_CNT 0x00000018 428#define R_SER_DMA_CUR_DSCRA 0x00000020 429#define R_SER_DMA_CUR_DSCRB 0x00000028 430#define R_SER_DMA_CUR_DSCRADDR 0x00000030 431 432#define R_SER_DMA_CONFIG0_RX 0x00000000 433#define R_SER_DMA_CONFIG1_RX 0x00000008 434#define R_SER_DMA_DSCR_BASE_RX 0x00000010 435#define R_SER_DMA_DSCR_COUNT_RX 0x00000018 436#define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 437#define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 438#define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 439 440#define R_SER_DMA_CONFIG0_TX 0x00000080 441#define R_SER_DMA_CONFIG1_TX 0x00000088 442#define R_SER_DMA_DSCR_BASE_TX 0x00000090 443#define R_SER_DMA_DSCR_COUNT_TX 0x00000098 444#define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 445#define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 446#define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 447 448#define R_SER_MODE 0x00000100 449#define R_SER_MINFRM_SZ 0x00000108 450#define R_SER_MAXFRM_SZ 0x00000110 451#define R_SER_ADDR 0x00000118 452#define R_SER_USR0_ADDR 0x00000120 453#define R_SER_USR1_ADDR 0x00000128 454#define R_SER_USR2_ADDR 0x00000130 455#define R_SER_USR3_ADDR 0x00000138 456#define R_SER_CMD 0x00000140 457#define R_SER_TX_RD_THRSH 0x00000160 458#define R_SER_TX_WR_THRSH 0x00000168 459#define R_SER_RX_RD_THRSH 0x00000170 460#define R_SER_LINE_MODE 0x00000178 461#define R_SER_DMA_ENABLE 0x00000180 462#define R_SER_INT_MASK 0x00000190 463#define R_SER_STATUS 0x00000188 464#define R_SER_STATUS_DEBUG 0x000001A8 465#define R_SER_RX_TABLE_BASE 0x00000200 466#define SER_RX_TABLE_COUNT 16 467#define R_SER_TX_TABLE_BASE 0x00000300 468#define SER_TX_TABLE_COUNT 16 469 470/* RMON Counters */ 471#define R_SER_RMON_TX_BYTE_LO 0x000001C0 472#define R_SER_RMON_TX_BYTE_HI 0x000001C8 473#define R_SER_RMON_RX_BYTE_LO 0x000001D0 474#define R_SER_RMON_RX_BYTE_HI 0x000001D8 475#define R_SER_RMON_TX_UNDERRUN 0x000001E0 476#define R_SER_RMON_RX_OVERFLOW 0x000001E8 477#define R_SER_RMON_RX_ERRORS 0x000001F0 478#define R_SER_RMON_RX_BADADDR 0x000001F8 479 480#endif /* 1250/112x */ 481 482/* ********************************************************************* 483 * Generic Bus Registers 484 ********************************************************************* */ 485 486#define IO_EXT_CFG_COUNT 8 487 488#define A_IO_EXT_BASE 0x0010061000 489#define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) 490 491#define A_IO_EXT_CFG_BASE 0x0010061000 492#define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 493#define A_IO_EXT_START_ADDR_BASE 0x0010061200 494#define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 495#define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 496 497#define IO_EXT_REGISTER_SPACING 8 498#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) 499#define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) 500 501#define R_IO_EXT_CFG 0x0000 502#define R_IO_EXT_MULT_SIZE 0x0100 503#define R_IO_EXT_START_ADDR 0x0200 504#define R_IO_EXT_TIME_CFG0 0x0600 505#define R_IO_EXT_TIME_CFG1 0x0700 506 507 508#define A_IO_INTERRUPT_STATUS 0x0010061A00 509#define A_IO_INTERRUPT_DATA0 0x0010061A10 510#define A_IO_INTERRUPT_DATA1 0x0010061A18 511#define A_IO_INTERRUPT_DATA2 0x0010061A20 512#define A_IO_INTERRUPT_DATA3 0x0010061A28 513#define A_IO_INTERRUPT_ADDR0 0x0010061A30 514#define A_IO_INTERRUPT_ADDR1 0x0010061A40 515#define A_IO_INTERRUPT_PARITY 0x0010061A50 516#define A_IO_PCMCIA_CFG 0x0010061A60 517#define A_IO_PCMCIA_STATUS 0x0010061A70 518#define A_IO_DRIVE_0 0x0010061300 519#define A_IO_DRIVE_1 0x0010061308 520#define A_IO_DRIVE_2 0x0010061310 521#define A_IO_DRIVE_3 0x0010061318 522#define A_IO_DRIVE_BASE A_IO_DRIVE_0 523#define IO_DRIVE_REGISTER_SPACING 8 524#define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) 525#define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) 526 527#define R_IO_INTERRUPT_STATUS 0x0A00 528#define R_IO_INTERRUPT_DATA0 0x0A10 529#define R_IO_INTERRUPT_DATA1 0x0A18 530#define R_IO_INTERRUPT_DATA2 0x0A20 531#define R_IO_INTERRUPT_DATA3 0x0A28 532#define R_IO_INTERRUPT_ADDR0 0x0A30 533#define R_IO_INTERRUPT_ADDR1 0x0A40 534#define R_IO_INTERRUPT_PARITY 0x0A50 535#define R_IO_PCMCIA_CFG 0x0A60 536#define R_IO_PCMCIA_STATUS 0x0A70 537 538/* ********************************************************************* 539 * GPIO Registers 540 ********************************************************************* */ 541 542#define A_GPIO_CLR_EDGE 0x0010061A80 543#define A_GPIO_INT_TYPE 0x0010061A88 544#define A_GPIO_INPUT_INVERT 0x0010061A90 545#define A_GPIO_GLITCH 0x0010061A98 546#define A_GPIO_READ 0x0010061AA0 547#define A_GPIO_DIRECTION 0x0010061AA8 548#define A_GPIO_PIN_CLR 0x0010061AB0 549#define A_GPIO_PIN_SET 0x0010061AB8 550 551#define A_GPIO_BASE 0x0010061A80 552 553#define R_GPIO_CLR_EDGE 0x00 554#define R_GPIO_INT_TYPE 0x08 555#define R_GPIO_INPUT_INVERT 0x10 556#define R_GPIO_GLITCH 0x18 557#define R_GPIO_READ 0x20 558#define R_GPIO_DIRECTION 0x28 559#define R_GPIO_PIN_CLR 0x30 560#define R_GPIO_PIN_SET 0x38 561 562/* ********************************************************************* 563 * SMBus Registers 564 ********************************************************************* */ 565 566#define A_SMB_XTRA_0 0x0010060000 567#define A_SMB_XTRA_1 0x0010060008 568#define A_SMB_FREQ_0 0x0010060010 569#define A_SMB_FREQ_1 0x0010060018 570#define A_SMB_STATUS_0 0x0010060020 571#define A_SMB_STATUS_1 0x0010060028 572#define A_SMB_CMD_0 0x0010060030 573#define A_SMB_CMD_1 0x0010060038 574#define A_SMB_START_0 0x0010060040 575#define A_SMB_START_1 0x0010060048 576#define A_SMB_DATA_0 0x0010060050 577#define A_SMB_DATA_1 0x0010060058 578#define A_SMB_CONTROL_0 0x0010060060 579#define A_SMB_CONTROL_1 0x0010060068 580#define A_SMB_PEC_0 0x0010060070 581#define A_SMB_PEC_1 0x0010060078 582 583#define A_SMB_0 0x0010060000 584#define A_SMB_1 0x0010060008 585#define SMB_REGISTER_SPACING 0x8 586#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) 587#define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg)) 588 589#define R_SMB_XTRA 0x0000000000 590#define R_SMB_FREQ 0x0000000010 591#define R_SMB_STATUS 0x0000000020 592#define R_SMB_CMD 0x0000000030 593#define R_SMB_START 0x0000000040 594#define R_SMB_DATA 0x0000000050 595#define R_SMB_CONTROL 0x0000000060 596#define R_SMB_PEC 0x0000000070 597 598/* ********************************************************************* 599 * Timer Registers 600 ********************************************************************* */ 601 602/* 603 * Watchdog timers 604 */ 605 606#define A_SCD_WDOG_0 0x0010020050 607#define A_SCD_WDOG_1 0x0010020150 608#define SCD_WDOG_SPACING 0x100 609#define SCD_NUM_WDOGS 2 610#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) 611#define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r)) 612 613#define R_SCD_WDOG_INIT 0x0000000000 614#define R_SCD_WDOG_CNT 0x0000000008 615#define R_SCD_WDOG_CFG 0x0000000010 616 617#define A_SCD_WDOG_INIT_0 0x0010020050 618#define A_SCD_WDOG_CNT_0 0x0010020058 619#define A_SCD_WDOG_CFG_0 0x0010020060 620 621#define A_SCD_WDOG_INIT_1 0x0010020150 622#define A_SCD_WDOG_CNT_1 0x0010020158 623#define A_SCD_WDOG_CFG_1 0x0010020160 624 625/* 626 * Generic timers 627 */ 628 629#define A_SCD_TIMER_0 0x0010020070 630#define A_SCD_TIMER_1 0x0010020078 631#define A_SCD_TIMER_2 0x0010020170 632#define A_SCD_TIMER_3 0x0010020178 633#define SCD_NUM_TIMERS 4 634#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) 635#define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r)) 636 637#define R_SCD_TIMER_INIT 0x0000000000 638#define R_SCD_TIMER_CNT 0x0000000010 639#define R_SCD_TIMER_CFG 0x0000000020 640 641#define A_SCD_TIMER_INIT_0 0x0010020070 642#define A_SCD_TIMER_CNT_0 0x0010020080 643#define A_SCD_TIMER_CFG_0 0x0010020090 644 645#define A_SCD_TIMER_INIT_1 0x0010020078 646#define A_SCD_TIMER_CNT_1 0x0010020088 647#define A_SCD_TIMER_CFG_1 0x0010020098 648 649#define A_SCD_TIMER_INIT_2 0x0010020170 650#define A_SCD_TIMER_CNT_2 0x0010020180 651#define A_SCD_TIMER_CFG_2 0x0010020190 652 653#define A_SCD_TIMER_INIT_3 0x0010020178 654#define A_SCD_TIMER_CNT_3 0x0010020188 655#define A_SCD_TIMER_CFG_3 0x0010020198 656 657#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 658#define A_SCD_SCRATCH 0x0010020C10 659#endif /* 1250 PASS2 || 112x PASS1 */ 660 661#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 662 SIBYTE_HDR_FEATURE_CHIP(1480) 663#define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 664#define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 665#define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 666#endif 667 668/* ********************************************************************* 669 * System Control Registers 670 ********************************************************************* */ 671 672#define A_SCD_SYSTEM_REVISION 0x0010020000 673#define A_SCD_SYSTEM_CFG 0x0010020008 674#define A_SCD_SYSTEM_MANUF 0x0010038000 675 676/* ********************************************************************* 677 * System Address Trap Registers 678 ********************************************************************* */ 679 680#define A_ADDR_TRAP_INDEX 0x00100200B0 681#define A_ADDR_TRAP_REG 0x00100200B8 682#define A_ADDR_TRAP_UP_0 0x0010020400 683#define A_ADDR_TRAP_UP_1 0x0010020408 684#define A_ADDR_TRAP_UP_2 0x0010020410 685#define A_ADDR_TRAP_UP_3 0x0010020418 686#define A_ADDR_TRAP_DOWN_0 0x0010020420 687#define A_ADDR_TRAP_DOWN_1 0x0010020428 688#define A_ADDR_TRAP_DOWN_2 0x0010020430 689#define A_ADDR_TRAP_DOWN_3 0x0010020438 690#define A_ADDR_TRAP_CFG_0 0x0010020440 691#define A_ADDR_TRAP_CFG_1 0x0010020448 692#define A_ADDR_TRAP_CFG_2 0x0010020450 693#define A_ADDR_TRAP_CFG_3 0x0010020458 694#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || \ 695 SIBYTE_HDR_FEATURE_CHIP(1480) 696#define A_ADDR_TRAP_REG_DEBUG 0x0010020460 697#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 698 699#define ADDR_TRAP_SPACING 8 700#define NUM_ADDR_TRAP 4 701#define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING)) 702#define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING)) 703#define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING)) 704 705 706/* ********************************************************************* 707 * System Interrupt Mapper Registers 708 ********************************************************************* */ 709 710#define A_IMR_CPU0_BASE 0x0010020000 711#define A_IMR_CPU1_BASE 0x0010022000 712#define IMR_REGISTER_SPACING 0x2000 713#define IMR_REGISTER_SPACING_SHIFT 13 714 715#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) 716#define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg)) 717 718#define R_IMR_INTERRUPT_DIAG 0x0010 719#define R_IMR_INTERRUPT_LDT 0x0018 720#define R_IMR_INTERRUPT_MASK 0x0028 721#define R_IMR_INTERRUPT_TRACE 0x0038 722#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 723#define R_IMR_LDT_INTERRUPT_SET 0x0048 724#define R_IMR_LDT_INTERRUPT 0x0018 725#define R_IMR_LDT_INTERRUPT_CLR 0x0020 726#define R_IMR_MAILBOX_CPU 0x00c0 727#define R_IMR_ALIAS_MAILBOX_CPU 0x1000 728#define R_IMR_MAILBOX_SET_CPU 0x00C8 729#define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 730#define R_IMR_MAILBOX_CLR_CPU 0x00D0 731#define R_IMR_INTERRUPT_STATUS_BASE 0x0100 732#define R_IMR_INTERRUPT_STATUS_COUNT 7 733#define R_IMR_INTERRUPT_MAP_BASE 0x0200 734#define R_IMR_INTERRUPT_MAP_COUNT 64 735 736/* 737 * these macros work together to build the address of a mailbox 738 * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1) 739 * for mbox_0_set_cpu2 returns 0x00100240C8 740 */ 741#define A_MAILBOX_REGISTER(reg,cpu) \ 742 (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg) 743 744/* ********************************************************************* 745 * System Performance Counter Registers 746 ********************************************************************* */ 747 748#define A_SCD_PERF_CNT_CFG 0x00100204C0 749#define A_SCD_PERF_CNT_0 0x00100204D0 750#define A_SCD_PERF_CNT_1 0x00100204D8 751#define A_SCD_PERF_CNT_2 0x00100204E0 752#define A_SCD_PERF_CNT_3 0x00100204E8 753 754#define SCD_NUM_PERF_CNT 4 755#define SCD_PERF_CNT_SPACING 8 756#define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING)) 757 758/* ********************************************************************* 759 * System Bus Watcher Registers 760 ********************************************************************* */ 761 762#define A_SCD_BUS_ERR_STATUS 0x0010020880 763#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 764#define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 765#define A_BUS_ERR_STATUS_DEBUG 0x00100208D0 766#endif /* 1250 PASS2 || 112x PASS1 */ 767#define A_BUS_ERR_DATA_0 0x00100208A0 768#define A_BUS_ERR_DATA_1 0x00100208A8 769#define A_BUS_ERR_DATA_2 0x00100208B0 770#define A_BUS_ERR_DATA_3 0x00100208B8 771#define A_BUS_L2_ERRORS 0x00100208C0 772#define A_BUS_MEM_IO_ERRORS 0x00100208C8 773 774/* ********************************************************************* 775 * System Debug Controller Registers 776 ********************************************************************* */ 777 778#define A_SCD_JTAG_BASE 0x0010000000 779 780/* ********************************************************************* 781 * System Trace Buffer Registers 782 ********************************************************************* */ 783 784#define A_SCD_TRACE_CFG 0x0010020A00 785#define A_SCD_TRACE_READ 0x0010020A08 786#define A_SCD_TRACE_EVENT_0 0x0010020A20 787#define A_SCD_TRACE_EVENT_1 0x0010020A28 788#define A_SCD_TRACE_EVENT_2 0x0010020A30 789#define A_SCD_TRACE_EVENT_3 0x0010020A38 790#define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 791#define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 792#define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 793#define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 794#define A_SCD_TRACE_EVENT_4 0x0010020A60 795#define A_SCD_TRACE_EVENT_5 0x0010020A68 796#define A_SCD_TRACE_EVENT_6 0x0010020A70 797#define A_SCD_TRACE_EVENT_7 0x0010020A78 798#define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 799#define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 800#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 801#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 802 803#define TRACE_REGISTER_SPACING 8 804#define TRACE_NUM_REGISTERS 8 805#define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \ 806 (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \ 807 (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING))) 808#define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \ 809 (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \ 810 (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING))) 811 812/* ********************************************************************* 813 * System Generic DMA Registers 814 ********************************************************************* */ 815 816#define A_DM_0 0x0010020B00 817#define A_DM_1 0x0010020B20 818#define A_DM_2 0x0010020B40 819#define A_DM_3 0x0010020B60 820#define DM_REGISTER_SPACING 0x20 821#define DM_NUM_CHANNELS 4 822#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) 823#define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg)) 824 825#define R_DM_DSCR_BASE 0x0000000000 826#define R_DM_DSCR_COUNT 0x0000000008 827#define R_DM_CUR_DSCR_ADDR 0x0000000010 828#define R_DM_DSCR_BASE_DEBUG 0x0000000018 829 830#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 831#define A_DM_PARTIAL_0 0x0010020ba0 832#define A_DM_PARTIAL_1 0x0010020ba8 833#define A_DM_PARTIAL_2 0x0010020bb0 834#define A_DM_PARTIAL_3 0x0010020bb8 835#define DM_PARTIAL_REGISTER_SPACING 0x8 836#define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING)) 837#endif /* 1250 PASS3 || 112x PASS1 */ 838 839#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 840#define A_DM_CRC_0 0x0010020b80 841#define A_DM_CRC_1 0x0010020b90 842#define DM_CRC_REGISTER_SPACING 0x10 843#define DM_CRC_NUM_CHANNELS 2 844#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) 845#define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC_BASE(idx) + (reg)) 846 847#define R_CRC_DEF_0 0x00 848#define R_CTCP_DEF_0 0x08 849#endif /* 1250 PASS3 || 112x PASS1 */ 850 851/* ********************************************************************* 852 * Physical Address Map 853 ********************************************************************* */ 854 855#if SIBYTE_HDR_FEATURE_1250_112x 856#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) 857#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) 858#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) 859#define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) 860#define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) 861#define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) 862#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) 863#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) 864#define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) 865#define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) 866#define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) 867#define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) 868#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) 869#define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) 870#define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) 871#define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) 872#define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) 873#define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) 874#define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) 875#define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) 876#define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) 877#define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) 878#define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) 879#define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) 880#define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) 881 882#define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) 883#define PHYS_L2CACHE_NUM_WAYS 4 884#define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) 885#define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) 886#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) 887#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) 888#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) 889#endif 890 891 892#endif 893