Searched refs:R_IMR_INTERRUPT_MASK (Results 1 - 7 of 7) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/sibyte/sb1250/
H A Dirq.c83 R_IMR_INTERRUPT_MASK));
86 R_IMR_INTERRUPT_MASK));
97 R_IMR_INTERRUPT_MASK));
100 R_IMR_INTERRUPT_MASK));
122 R_IMR_INTERRUPT_MASK));
128 R_IMR_INTERRUPT_MASK));
134 R_IMR_INTERRUPT_MASK));
137 R_IMR_INTERRUPT_MASK));
290 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
291 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/sibyte/sb1250/
H A Dirq.c83 R_IMR_INTERRUPT_MASK));
86 R_IMR_INTERRUPT_MASK));
97 R_IMR_INTERRUPT_MASK));
100 R_IMR_INTERRUPT_MASK));
122 R_IMR_INTERRUPT_MASK));
128 R_IMR_INTERRUPT_MASK));
134 R_IMR_INTERRUPT_MASK));
137 R_IMR_INTERRUPT_MASK));
290 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
291 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
[all...]
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/src/
H A Dsb1250_irq.c210 *IMR_POINTER(0, R_IMR_INTERRUPT_MASK) = ~((uint64_t)0);
211 *IMR_POINTER(1, R_IMR_INTERRUPT_MASK) = ~((uint64_t)0);
241 *IMR_POINTER(cpu, R_IMR_INTERRUPT_MASK) |= ((uint64_t)1 << irq);
257 *IMR_POINTER(cpu, R_IMR_INTERRUPT_MASK) &=~ ((uint64_t)1 << irq);
276 *IMR_POINTER(0, R_IMR_INTERRUPT_MASK) &=~ ((uint64_t)1 << irq);
299 *IMR_POINTER(0, R_IMR_INTERRUPT_MASK) |= ((uint64_t)1 << irq);
H A Dsb1250_ircpoll.S164 ld a1, R_IMR_INTERRUPT_MASK(v0)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/
H A Dsb1250_regs.h698 #define R_IMR_INTERRUPT_MASK 0x0028 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/sibyte/
H A Dsb1250_regs.h720 #define R_IMR_INTERRUPT_MASK 0x0028 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/sibyte/
H A Dsb1250_regs.h720 #define R_IMR_INTERRUPT_MASK 0x0028 macro

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