Searched refs:PORT_PLCR (Results 1 - 14 of 14) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/include/mach-common/mach/
H A Dsh7763rdp.h35 #define PORT_PLCR 0xFFEF0016 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/include/mach-common/mach/
H A Dsh7763rdp.h35 #define PORT_PLCR 0xFFEF0016 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/include/cpu-sh3/cpu/
H A Dgpio.h28 #define PORT_PLCR 0xA4050114UL macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/include/cpu-sh3/cpu/
H A Dgpio.h28 #define PORT_PLCR 0xA4050114UL macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/include/mach-se/mach/
H A Dse7722.h69 #define PORT_PLCR 0xA4050114UL macro
H A Dse7343.h72 #define PORT_PLCR 0xA4050114 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/include/mach-se/mach/
H A Dse7722.h69 #define PORT_PLCR 0xA4050114UL macro
H A Dse7343.h72 #define PORT_PLCR 0xA4050114 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/boards/mach-se/7722/
H A Dsetup.c174 __raw_writew(0x0000, PORT_PLCR);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/boards/mach-sh7763rdp/
H A Dsetup.c180 __raw_writew(0, PORT_PLCR);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/boards/mach-se/7722/
H A Dsetup.c174 __raw_writew(0x0000, PORT_PLCR);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/boards/mach-sh7763rdp/
H A Dsetup.c180 __raw_writew(0, PORT_PLCR);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/boards/
H A Dboard-magicpanelr2.c147 __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/boards/
H A Dboard-magicpanelr2.c147 __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */

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