Searched refs:PORT_PKCR (Results 1 - 14 of 14) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/include/mach-common/mach/
H A Dsh7763rdp.h34 #define PORT_PKCR 0xFFEF0014 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/include/mach-common/mach/
H A Dsh7763rdp.h34 #define PORT_PKCR 0xFFEF0014 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/include/cpu-sh3/cpu/
H A Dgpio.h27 #define PORT_PKCR 0xA4050112UL macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/include/cpu-sh3/cpu/
H A Dgpio.h27 #define PORT_PKCR 0xA4050112UL macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/include/mach-se/mach/
H A Dse7722.h67 #define PORT_PKCR 0xA4050112UL macro
H A Dse7343.h71 #define PORT_PKCR 0xA4050112 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/include/mach-se/mach/
H A Dse7722.h67 #define PORT_PKCR 0xA4050112UL macro
H A Dse7343.h71 #define PORT_PKCR 0xA4050112 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/boards/mach-se/7722/
H A Dsetup.c170 __raw_writew(0x0000, PORT_PKCR);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/boards/mach-sh7763rdp/
H A Dsetup.c179 __raw_writew(0, PORT_PKCR);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/boards/mach-se/7722/
H A Dsetup.c170 __raw_writew(0x0000, PORT_PKCR);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/boards/mach-sh7763rdp/
H A Dsetup.c179 __raw_writew(0, PORT_PKCR);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/boards/
H A Dboard-magicpanelr2.c142 __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/boards/
H A Dboard-magicpanelr2.c142 __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */

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