Searched refs:PLL_MOD (Results 1 - 25 of 30) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-omap2/
H A Dclkt2xxx_apll.c52 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
59 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
86 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
88 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
109 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
H A Dclkt2xxx_dpllcore.c38 v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
57 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
95 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
120 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
H A Dpowerdomains34xx.h238 .prcm_offs = PLL_MOD,
244 .prcm_offs = PLL_MOD,
250 .prcm_offs = PLL_MOD,
H A Dprcm.c317 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
319 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
321 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
323 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
470 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
472 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
474 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
476 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
H A Dcontrol.c243 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
245 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
247 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
249 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
251 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
H A Dprcm-common.h25 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
33 #define PLL_MOD 0x500 macro
45 #define OMAP3430_CCR_MOD PLL_MOD
H A Dsram242x.S123 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
217 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
310 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
312 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
314 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
H A Dsram243x.S123 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
217 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
310 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
312 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
314 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
H A Dclock3xxx_data.c409 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
415 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
420 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
422 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
498 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
546 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
567 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
573 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
579 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
581 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLES
[all...]
H A Dclock2430_data.c102 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
107 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
132 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
143 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
175 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
212 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
242 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
1942 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
H A Dpm-debug.c147 { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
161 { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
H A Dclock2420_data.c102 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
107 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
132 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
143 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
175 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
221 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
1853 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
H A Dpm34xx.c877 PLL_MOD,
880 PLL_MOD,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-omap2/
H A Dclkt2xxx_apll.c52 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
59 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
86 cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN);
88 cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
109 aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
H A Dclkt2xxx_dpllcore.c38 v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
57 core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
95 mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
120 tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
H A Dpowerdomains34xx.h238 .prcm_offs = PLL_MOD,
244 .prcm_offs = PLL_MOD,
250 .prcm_offs = PLL_MOD,
H A Dprcm.c317 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
319 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
321 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
323 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
470 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
472 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
474 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
476 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
H A Dcontrol.c243 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
245 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL);
247 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
249 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
251 cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
H A Dprcm-common.h25 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
33 #define PLL_MOD 0x500 macro
45 #define OMAP3430_CCR_MOD PLL_MOD
H A Dsram242x.S123 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
217 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
310 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
312 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
314 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
H A Dsram243x.S123 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
217 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
310 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
312 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
314 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
H A Dclock3xxx_data.c409 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
415 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
420 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
422 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
498 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
546 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
567 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
573 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
579 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
581 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLES
[all...]
H A Dclock2430_data.c102 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
107 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
132 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
143 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
175 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
212 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
242 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
1942 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
H A Dpm-debug.c147 { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
161 { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
H A Dclock2420_data.c102 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
107 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
132 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
143 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
175 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
221 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
1853 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);

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