1/* 2 * linux/arch/arm/mach-omap2/prcm.c 3 * 4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions 5 * 6 * Copyright (C) 2005 Nokia Corporation 7 * 8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 9 * 10 * Copyright (C) 2007 Texas Instruments, Inc. 11 * Rajendra Nayak <rnayak@ti.com> 12 * 13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc. 14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com> 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License version 2 as 18 * published by the Free Software Foundation. 19 */ 20#include <linux/module.h> 21#include <linux/init.h> 22#include <linux/clk.h> 23#include <linux/io.h> 24#include <linux/delay.h> 25 26#include <plat/common.h> 27#include <plat/prcm.h> 28#include <plat/irqs.h> 29#include <plat/control.h> 30 31#include "clock.h" 32#include "clock2xxx.h" 33#include "cm.h" 34#include "prm.h" 35#include "prm-regbits-24xx.h" 36 37static void __iomem *prm_base; 38static void __iomem *cm_base; 39static void __iomem *cm2_base; 40 41#define MAX_MODULE_ENABLE_WAIT 100000 42 43struct omap3_prcm_regs { 44 u32 control_padconf_sys_nirq; 45 u32 iva2_cm_clksel1; 46 u32 iva2_cm_clksel2; 47 u32 cm_sysconfig; 48 u32 sgx_cm_clksel; 49 u32 dss_cm_clksel; 50 u32 cam_cm_clksel; 51 u32 per_cm_clksel; 52 u32 emu_cm_clksel; 53 u32 emu_cm_clkstctrl; 54 u32 pll_cm_autoidle2; 55 u32 pll_cm_clksel4; 56 u32 pll_cm_clksel5; 57 u32 pll_cm_clken2; 58 u32 cm_polctrl; 59 u32 iva2_cm_fclken; 60 u32 iva2_cm_clken_pll; 61 u32 core_cm_fclken1; 62 u32 core_cm_fclken3; 63 u32 sgx_cm_fclken; 64 u32 wkup_cm_fclken; 65 u32 dss_cm_fclken; 66 u32 cam_cm_fclken; 67 u32 per_cm_fclken; 68 u32 usbhost_cm_fclken; 69 u32 core_cm_iclken1; 70 u32 core_cm_iclken2; 71 u32 core_cm_iclken3; 72 u32 sgx_cm_iclken; 73 u32 wkup_cm_iclken; 74 u32 dss_cm_iclken; 75 u32 cam_cm_iclken; 76 u32 per_cm_iclken; 77 u32 usbhost_cm_iclken; 78 u32 iva2_cm_autiidle2; 79 u32 mpu_cm_autoidle2; 80 u32 iva2_cm_clkstctrl; 81 u32 mpu_cm_clkstctrl; 82 u32 core_cm_clkstctrl; 83 u32 sgx_cm_clkstctrl; 84 u32 dss_cm_clkstctrl; 85 u32 cam_cm_clkstctrl; 86 u32 per_cm_clkstctrl; 87 u32 neon_cm_clkstctrl; 88 u32 usbhost_cm_clkstctrl; 89 u32 core_cm_autoidle1; 90 u32 core_cm_autoidle2; 91 u32 core_cm_autoidle3; 92 u32 wkup_cm_autoidle; 93 u32 dss_cm_autoidle; 94 u32 cam_cm_autoidle; 95 u32 per_cm_autoidle; 96 u32 usbhost_cm_autoidle; 97 u32 sgx_cm_sleepdep; 98 u32 dss_cm_sleepdep; 99 u32 cam_cm_sleepdep; 100 u32 per_cm_sleepdep; 101 u32 usbhost_cm_sleepdep; 102 u32 cm_clkout_ctrl; 103 u32 prm_clkout_ctrl; 104 u32 sgx_pm_wkdep; 105 u32 dss_pm_wkdep; 106 u32 cam_pm_wkdep; 107 u32 per_pm_wkdep; 108 u32 neon_pm_wkdep; 109 u32 usbhost_pm_wkdep; 110 u32 core_pm_mpugrpsel1; 111 u32 iva2_pm_ivagrpsel1; 112 u32 core_pm_mpugrpsel3; 113 u32 core_pm_ivagrpsel3; 114 u32 wkup_pm_mpugrpsel; 115 u32 wkup_pm_ivagrpsel; 116 u32 per_pm_mpugrpsel; 117 u32 per_pm_ivagrpsel; 118 u32 wkup_pm_wken; 119}; 120 121struct omap3_prcm_regs prcm_context; 122 123u32 omap_prcm_get_reset_sources(void) 124{ 125 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 126 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; 127 if (cpu_is_omap44xx()) 128 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; 129 130 return 0; 131} 132EXPORT_SYMBOL(omap_prcm_get_reset_sources); 133 134/* Resets clock rates and reboots the system. Only called from system.h */ 135void omap_prcm_arch_reset(char mode, const char *cmd) 136{ 137 s16 prcm_offs = 0; 138 139 if (cpu_is_omap24xx()) { 140 omap2xxx_clk_prepare_for_reboot(); 141 142 prcm_offs = WKUP_MOD; 143 } else if (cpu_is_omap34xx()) { 144 u32 l; 145 146 prcm_offs = OMAP3430_GR_MOD; 147 l = ('B' << 24) | ('M' << 16) | (cmd ? (u8)*cmd : 0); 148 /* Reserve the first word in scratchpad for communicating 149 * with the boot ROM. A pointer to a data structure 150 * describing the boot process can be stored there, 151 * cf. OMAP34xx TRM, Initialization / Software Booting 152 * Configuration. */ 153 omap_writel(l, OMAP343X_SCRATCHPAD + 4); 154 } else if (cpu_is_omap44xx()) 155 prcm_offs = OMAP4430_PRM_DEVICE_MOD; 156 else 157 WARN_ON(1); 158 159 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 160 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, 161 OMAP2_RM_RSTCTRL); 162 if (cpu_is_omap44xx()) 163 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, 164 OMAP4_RM_RSTCTRL); 165} 166 167static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) 168{ 169 BUG_ON(!base); 170 return __raw_readl(base + module + reg); 171} 172 173static inline void __omap_prcm_write(u32 value, void __iomem *base, 174 s16 module, u16 reg) 175{ 176 BUG_ON(!base); 177 __raw_writel(value, base + module + reg); 178} 179 180/* Read a register in a PRM module */ 181u32 prm_read_mod_reg(s16 module, u16 idx) 182{ 183 return __omap_prcm_read(prm_base, module, idx); 184} 185 186/* Write into a register in a PRM module */ 187void prm_write_mod_reg(u32 val, s16 module, u16 idx) 188{ 189 __omap_prcm_write(val, prm_base, module, idx); 190} 191 192/* Read-modify-write a register in a PRM module. Caller must lock */ 193u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) 194{ 195 u32 v; 196 197 v = prm_read_mod_reg(module, idx); 198 v &= ~mask; 199 v |= bits; 200 prm_write_mod_reg(v, module, idx); 201 202 return v; 203} 204 205/* Read a PRM register, AND it, and shift the result down to bit 0 */ 206u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) 207{ 208 u32 v; 209 210 v = prm_read_mod_reg(domain, idx); 211 v &= mask; 212 v >>= __ffs(mask); 213 214 return v; 215} 216 217/* Read a register in a CM module */ 218u32 cm_read_mod_reg(s16 module, u16 idx) 219{ 220 return __omap_prcm_read(cm_base, module, idx); 221} 222 223/* Write into a register in a CM module */ 224void cm_write_mod_reg(u32 val, s16 module, u16 idx) 225{ 226 __omap_prcm_write(val, cm_base, module, idx); 227} 228 229/* Read-modify-write a register in a CM module. Caller must lock */ 230u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) 231{ 232 u32 v; 233 234 v = cm_read_mod_reg(module, idx); 235 v &= ~mask; 236 v |= bits; 237 cm_write_mod_reg(v, module, idx); 238 239 return v; 240} 241 242/** 243 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness 244 * @reg: physical address of module IDLEST register 245 * @mask: value to mask against to determine if the module is active 246 * @idlest: idle state indicator (0 or 1) for the clock 247 * @name: name of the clock (for printk) 248 * 249 * Returns 1 if the module indicated readiness in time, or 0 if it 250 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. 251 */ 252int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, 253 const char *name) 254{ 255 int i = 0; 256 int ena = 0; 257 258 if (idlest) 259 ena = 0; 260 else 261 ena = mask; 262 263 /* Wait for lock */ 264 omap_test_timeout(((__raw_readl(reg) & mask) == ena), 265 MAX_MODULE_ENABLE_WAIT, i); 266 267 if (i < MAX_MODULE_ENABLE_WAIT) 268 pr_debug("cm: Module associated with clock %s ready after %d " 269 "loops\n", name, i); 270 else 271 pr_err("cm: Module associated with clock %s didn't enable in " 272 "%d tries\n", name, MAX_MODULE_ENABLE_WAIT); 273 274 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0; 275}; 276 277void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) 278{ 279 /* Static mapping, never released */ 280 if (omap2_globals->prm) { 281 prm_base = ioremap(omap2_globals->prm, SZ_8K); 282 WARN_ON(!prm_base); 283 } 284 if (omap2_globals->cm) { 285 cm_base = ioremap(omap2_globals->cm, SZ_8K); 286 WARN_ON(!cm_base); 287 } 288 if (omap2_globals->cm2) { 289 cm2_base = ioremap(omap2_globals->cm2, SZ_8K); 290 WARN_ON(!cm2_base); 291 } 292} 293 294#ifdef CONFIG_ARCH_OMAP3 295void omap3_prcm_save_context(void) 296{ 297 prcm_context.control_padconf_sys_nirq = 298 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); 299 prcm_context.iva2_cm_clksel1 = 300 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); 301 prcm_context.iva2_cm_clksel2 = 302 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); 303 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); 304 prcm_context.sgx_cm_clksel = 305 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); 306 prcm_context.dss_cm_clksel = 307 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); 308 prcm_context.cam_cm_clksel = 309 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); 310 prcm_context.per_cm_clksel = 311 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); 312 prcm_context.emu_cm_clksel = 313 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); 314 prcm_context.emu_cm_clkstctrl = 315 cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); 316 prcm_context.pll_cm_autoidle2 = 317 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); 318 prcm_context.pll_cm_clksel4 = 319 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); 320 prcm_context.pll_cm_clksel5 = 321 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); 322 prcm_context.pll_cm_clken2 = 323 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); 324 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); 325 prcm_context.iva2_cm_fclken = 326 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); 327 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD, 328 OMAP3430_CM_CLKEN_PLL); 329 prcm_context.core_cm_fclken1 = 330 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 331 prcm_context.core_cm_fclken3 = 332 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); 333 prcm_context.sgx_cm_fclken = 334 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); 335 prcm_context.wkup_cm_fclken = 336 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); 337 prcm_context.dss_cm_fclken = 338 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); 339 prcm_context.cam_cm_fclken = 340 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); 341 prcm_context.per_cm_fclken = 342 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); 343 prcm_context.usbhost_cm_fclken = 344 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); 345 prcm_context.core_cm_iclken1 = 346 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); 347 prcm_context.core_cm_iclken2 = 348 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); 349 prcm_context.core_cm_iclken3 = 350 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); 351 prcm_context.sgx_cm_iclken = 352 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); 353 prcm_context.wkup_cm_iclken = 354 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); 355 prcm_context.dss_cm_iclken = 356 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); 357 prcm_context.cam_cm_iclken = 358 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); 359 prcm_context.per_cm_iclken = 360 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); 361 prcm_context.usbhost_cm_iclken = 362 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); 363 prcm_context.iva2_cm_autiidle2 = 364 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); 365 prcm_context.mpu_cm_autoidle2 = 366 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); 367 prcm_context.iva2_cm_clkstctrl = 368 cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); 369 prcm_context.mpu_cm_clkstctrl = 370 cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); 371 prcm_context.core_cm_clkstctrl = 372 cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); 373 prcm_context.sgx_cm_clkstctrl = 374 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, 375 OMAP2_CM_CLKSTCTRL); 376 prcm_context.dss_cm_clkstctrl = 377 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); 378 prcm_context.cam_cm_clkstctrl = 379 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); 380 prcm_context.per_cm_clkstctrl = 381 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); 382 prcm_context.neon_cm_clkstctrl = 383 cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); 384 prcm_context.usbhost_cm_clkstctrl = 385 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, 386 OMAP2_CM_CLKSTCTRL); 387 prcm_context.core_cm_autoidle1 = 388 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); 389 prcm_context.core_cm_autoidle2 = 390 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); 391 prcm_context.core_cm_autoidle3 = 392 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); 393 prcm_context.wkup_cm_autoidle = 394 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); 395 prcm_context.dss_cm_autoidle = 396 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); 397 prcm_context.cam_cm_autoidle = 398 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); 399 prcm_context.per_cm_autoidle = 400 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); 401 prcm_context.usbhost_cm_autoidle = 402 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); 403 prcm_context.sgx_cm_sleepdep = 404 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP); 405 prcm_context.dss_cm_sleepdep = 406 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); 407 prcm_context.cam_cm_sleepdep = 408 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); 409 prcm_context.per_cm_sleepdep = 410 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); 411 prcm_context.usbhost_cm_sleepdep = 412 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); 413 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD, 414 OMAP3_CM_CLKOUT_CTRL_OFFSET); 415 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD, 416 OMAP3_PRM_CLKOUT_CTRL_OFFSET); 417 prcm_context.sgx_pm_wkdep = 418 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP); 419 prcm_context.dss_pm_wkdep = 420 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP); 421 prcm_context.cam_pm_wkdep = 422 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP); 423 prcm_context.per_pm_wkdep = 424 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP); 425 prcm_context.neon_pm_wkdep = 426 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP); 427 prcm_context.usbhost_pm_wkdep = 428 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 429 prcm_context.core_pm_mpugrpsel1 = 430 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1); 431 prcm_context.iva2_pm_ivagrpsel1 = 432 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1); 433 prcm_context.core_pm_mpugrpsel3 = 434 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3); 435 prcm_context.core_pm_ivagrpsel3 = 436 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); 437 prcm_context.wkup_pm_mpugrpsel = 438 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL); 439 prcm_context.wkup_pm_ivagrpsel = 440 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL); 441 prcm_context.per_pm_mpugrpsel = 442 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); 443 prcm_context.per_pm_ivagrpsel = 444 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); 445 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN); 446 return; 447} 448 449void omap3_prcm_restore_context(void) 450{ 451 omap_ctrl_writel(prcm_context.control_padconf_sys_nirq, 452 OMAP343X_CONTROL_PADCONF_SYSNIRQ); 453 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, 454 CM_CLKSEL1); 455 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, 456 CM_CLKSEL2); 457 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); 458 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, 459 CM_CLKSEL); 460 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD, 461 CM_CLKSEL); 462 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD, 463 CM_CLKSEL); 464 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD, 465 CM_CLKSEL); 466 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD, 467 CM_CLKSEL1); 468 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, 469 OMAP2_CM_CLKSTCTRL); 470 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD, 471 CM_AUTOIDLE2); 472 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD, 473 OMAP3430ES2_CM_CLKSEL4); 474 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD, 475 OMAP3430ES2_CM_CLKSEL5); 476 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD, 477 OMAP3430ES2_CM_CLKEN2); 478 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL); 479 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, 480 CM_FCLKEN); 481 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, 482 OMAP3430_CM_CLKEN_PLL); 483 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1); 484 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD, 485 OMAP3430ES2_CM_FCLKEN3); 486 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, 487 CM_FCLKEN); 488 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); 489 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD, 490 CM_FCLKEN); 491 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD, 492 CM_FCLKEN); 493 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD, 494 CM_FCLKEN); 495 cm_write_mod_reg(prcm_context.usbhost_cm_fclken, 496 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); 497 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1); 498 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2); 499 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3); 500 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, 501 CM_ICLKEN); 502 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); 503 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD, 504 CM_ICLKEN); 505 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD, 506 CM_ICLKEN); 507 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD, 508 CM_ICLKEN); 509 cm_write_mod_reg(prcm_context.usbhost_cm_iclken, 510 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); 511 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD, 512 CM_AUTOIDLE2); 513 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); 514 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, 515 OMAP2_CM_CLKSTCTRL); 516 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, 517 OMAP2_CM_CLKSTCTRL); 518 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD, 519 OMAP2_CM_CLKSTCTRL); 520 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, 521 OMAP2_CM_CLKSTCTRL); 522 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, 523 OMAP2_CM_CLKSTCTRL); 524 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, 525 OMAP2_CM_CLKSTCTRL); 526 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, 527 OMAP2_CM_CLKSTCTRL); 528 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, 529 OMAP2_CM_CLKSTCTRL); 530 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl, 531 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); 532 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD, 533 CM_AUTOIDLE1); 534 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD, 535 CM_AUTOIDLE2); 536 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD, 537 CM_AUTOIDLE3); 538 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE); 539 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, 540 CM_AUTOIDLE); 541 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, 542 CM_AUTOIDLE); 543 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD, 544 CM_AUTOIDLE); 545 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle, 546 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); 547 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, 548 OMAP3430_CM_SLEEPDEP); 549 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, 550 OMAP3430_CM_SLEEPDEP); 551 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, 552 OMAP3430_CM_SLEEPDEP); 553 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD, 554 OMAP3430_CM_SLEEPDEP); 555 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep, 556 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); 557 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, 558 OMAP3_CM_CLKOUT_CTRL_OFFSET); 559 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD, 560 OMAP3_PRM_CLKOUT_CTRL_OFFSET); 561 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD, 562 PM_WKDEP); 563 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD, 564 PM_WKDEP); 565 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD, 566 PM_WKDEP); 567 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD, 568 PM_WKDEP); 569 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD, 570 PM_WKDEP); 571 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep, 572 OMAP3430ES2_USBHOST_MOD, PM_WKDEP); 573 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD, 574 OMAP3430_PM_MPUGRPSEL1); 575 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD, 576 OMAP3430_PM_IVAGRPSEL1); 577 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD, 578 OMAP3430ES2_PM_MPUGRPSEL3); 579 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD, 580 OMAP3430ES2_PM_IVAGRPSEL3); 581 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD, 582 OMAP3430_PM_MPUGRPSEL); 583 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD, 584 OMAP3430_PM_IVAGRPSEL); 585 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD, 586 OMAP3430_PM_MPUGRPSEL); 587 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD, 588 OMAP3430_PM_IVAGRPSEL); 589 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN); 590 return; 591} 592#endif 593