1#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H 2#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H 3 4/* 5 * OMAP2/3 PRCM base and module definitions 6 * 7 * Copyright (C) 2007-2009 Texas Instruments, Inc. 8 * Copyright (C) 2007-2009 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * OMAP4 defines in this file are automatically generated from the OMAP hardware 12 * databases. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 19 20/* Module offsets from both CM_BASE & PRM_BASE */ 21 22/* 23 * Offsets that are the same on 24xx and 34xx 24 * 25 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is 26 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. 27 */ 28#define OCP_MOD 0x000 29#define MPU_MOD 0x100 30#define CORE_MOD 0x200 31#define GFX_MOD 0x300 32#define WKUP_MOD 0x400 33#define PLL_MOD 0x500 34 35 36/* Chip-specific module offsets */ 37#define OMAP24XX_GR_MOD OCP_MOD 38#define OMAP24XX_DSP_MOD 0x800 39 40#define OMAP2430_MDM_MOD 0xc00 41 42/* IVA2 module is < base on 3430 */ 43#define OMAP3430_IVA2_MOD -0x800 44#define OMAP3430ES2_SGX_MOD GFX_MOD 45#define OMAP3430_CCR_MOD PLL_MOD 46#define OMAP3430_DSS_MOD 0x600 47#define OMAP3430_CAM_MOD 0x700 48#define OMAP3430_PER_MOD 0x800 49#define OMAP3430_EMU_MOD 0x900 50#define OMAP3430_GR_MOD 0xa00 51#define OMAP3430_NEON_MOD 0xb00 52#define OMAP3430ES2_USBHOST_MOD 0xc00 53 54#define BITS(n_bit) \ 55 (((1 << n_bit) - 1) | (1 << n_bit)) 56 57#define BITFIELD(l_bit, u_bit) \ 58 (BITS(u_bit) & ~((BITS(l_bit)) >> 1)) 59 60/* OMAP44XX specific module offsets */ 61 62/* CM1 instances */ 63 64#define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000 65#define OMAP4430_CM1_CKGEN_MOD 0x0100 66#define OMAP4430_CM1_MPU_MOD 0x0300 67#define OMAP4430_CM1_TESLA_MOD 0x0400 68#define OMAP4430_CM1_ABE_MOD 0x0500 69#define OMAP4430_CM1_RESTORE_MOD 0x0e00 70#define OMAP4430_CM1_INSTR_MOD 0x0f00 71 72/* CM2 instances */ 73 74#define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000 75#define OMAP4430_CM2_CKGEN_MOD 0x0100 76#define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600 77#define OMAP4430_CM2_CORE_MOD 0x0700 78#define OMAP4430_CM2_IVAHD_MOD 0x0f00 79#define OMAP4430_CM2_CAM_MOD 0x1000 80#define OMAP4430_CM2_DSS_MOD 0x1100 81#define OMAP4430_CM2_GFX_MOD 0x1200 82#define OMAP4430_CM2_L3INIT_MOD 0x1300 83#define OMAP4430_CM2_L4PER_MOD 0x1400 84#define OMAP4430_CM2_CEFUSE_MOD 0x1600 85#define OMAP4430_CM2_RESTORE_MOD 0x1e00 86#define OMAP4430_CM2_INSTR_MOD 0x1f00 87 88/* PRM instances */ 89 90#define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000 91#define OMAP4430_PRM_CKGEN_MOD 0x0100 92#define OMAP4430_PRM_MPU_MOD 0x0300 93#define OMAP4430_PRM_TESLA_MOD 0x0400 94#define OMAP4430_PRM_ABE_MOD 0x0500 95#define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600 96#define OMAP4430_PRM_CORE_MOD 0x0700 97#define OMAP4430_PRM_IVAHD_MOD 0x0f00 98#define OMAP4430_PRM_CAM_MOD 0x1000 99#define OMAP4430_PRM_DSS_MOD 0x1100 100#define OMAP4430_PRM_GFX_MOD 0x1200 101#define OMAP4430_PRM_L3INIT_MOD 0x1300 102#define OMAP4430_PRM_L4PER_MOD 0x1400 103#define OMAP4430_PRM_CEFUSE_MOD 0x1600 104#define OMAP4430_PRM_WKUP_MOD 0x1700 105#define OMAP4430_PRM_WKUP_CM_MOD 0x1800 106#define OMAP4430_PRM_EMU_MOD 0x1900 107#define OMAP4430_PRM_EMU_CM_MOD 0x1a00 108#define OMAP4430_PRM_DEVICE_MOD 0x1b00 109#define OMAP4430_PRM_INSTR_MOD 0x1f00 110 111/* SCRM instances */ 112 113#define OMAP4430_SCRM_SCRM_MOD 0x0000 114 115/* PRCM_MPU instances */ 116 117#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD 0x0000 118#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200 119#define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400 120#define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800 121 122 123/* 24XX register bits shared between CM & PRM registers */ 124 125/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 126#define OMAP2420_EN_MMC_SHIFT 26 127#define OMAP2420_EN_MMC_MASK (1 << 26) 128#define OMAP24XX_EN_UART2_SHIFT 22 129#define OMAP24XX_EN_UART2_MASK (1 << 22) 130#define OMAP24XX_EN_UART1_SHIFT 21 131#define OMAP24XX_EN_UART1_MASK (1 << 21) 132#define OMAP24XX_EN_MCSPI2_SHIFT 18 133#define OMAP24XX_EN_MCSPI2_MASK (1 << 18) 134#define OMAP24XX_EN_MCSPI1_SHIFT 17 135#define OMAP24XX_EN_MCSPI1_MASK (1 << 17) 136#define OMAP24XX_EN_MCBSP2_SHIFT 16 137#define OMAP24XX_EN_MCBSP2_MASK (1 << 16) 138#define OMAP24XX_EN_MCBSP1_SHIFT 15 139#define OMAP24XX_EN_MCBSP1_MASK (1 << 15) 140#define OMAP24XX_EN_GPT12_SHIFT 14 141#define OMAP24XX_EN_GPT12_MASK (1 << 14) 142#define OMAP24XX_EN_GPT11_SHIFT 13 143#define OMAP24XX_EN_GPT11_MASK (1 << 13) 144#define OMAP24XX_EN_GPT10_SHIFT 12 145#define OMAP24XX_EN_GPT10_MASK (1 << 12) 146#define OMAP24XX_EN_GPT9_SHIFT 11 147#define OMAP24XX_EN_GPT9_MASK (1 << 11) 148#define OMAP24XX_EN_GPT8_SHIFT 10 149#define OMAP24XX_EN_GPT8_MASK (1 << 10) 150#define OMAP24XX_EN_GPT7_SHIFT 9 151#define OMAP24XX_EN_GPT7_MASK (1 << 9) 152#define OMAP24XX_EN_GPT6_SHIFT 8 153#define OMAP24XX_EN_GPT6_MASK (1 << 8) 154#define OMAP24XX_EN_GPT5_SHIFT 7 155#define OMAP24XX_EN_GPT5_MASK (1 << 7) 156#define OMAP24XX_EN_GPT4_SHIFT 6 157#define OMAP24XX_EN_GPT4_MASK (1 << 6) 158#define OMAP24XX_EN_GPT3_SHIFT 5 159#define OMAP24XX_EN_GPT3_MASK (1 << 5) 160#define OMAP24XX_EN_GPT2_SHIFT 4 161#define OMAP24XX_EN_GPT2_MASK (1 << 4) 162#define OMAP2420_EN_VLYNQ_SHIFT 3 163#define OMAP2420_EN_VLYNQ_MASK (1 << 3) 164 165/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 166#define OMAP2430_EN_GPIO5_SHIFT 10 167#define OMAP2430_EN_GPIO5_MASK (1 << 10) 168#define OMAP2430_EN_MCSPI3_SHIFT 9 169#define OMAP2430_EN_MCSPI3_MASK (1 << 9) 170#define OMAP2430_EN_MMCHS2_SHIFT 8 171#define OMAP2430_EN_MMCHS2_MASK (1 << 8) 172#define OMAP2430_EN_MMCHS1_SHIFT 7 173#define OMAP2430_EN_MMCHS1_MASK (1 << 7) 174#define OMAP24XX_EN_UART3_SHIFT 2 175#define OMAP24XX_EN_UART3_MASK (1 << 2) 176#define OMAP24XX_EN_USB_SHIFT 0 177#define OMAP24XX_EN_USB_MASK (1 << 0) 178 179/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 180#define OMAP2430_EN_MDM_INTC_SHIFT 11 181#define OMAP2430_EN_MDM_INTC_MASK (1 << 11) 182#define OMAP2430_EN_USBHS_SHIFT 6 183#define OMAP2430_EN_USBHS_MASK (1 << 6) 184 185/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ 186#define OMAP2420_ST_MMC_SHIFT 26 187#define OMAP2420_ST_MMC_MASK (1 << 26) 188#define OMAP24XX_ST_UART2_SHIFT 22 189#define OMAP24XX_ST_UART2_MASK (1 << 22) 190#define OMAP24XX_ST_UART1_SHIFT 21 191#define OMAP24XX_ST_UART1_MASK (1 << 21) 192#define OMAP24XX_ST_MCSPI2_SHIFT 18 193#define OMAP24XX_ST_MCSPI2_MASK (1 << 18) 194#define OMAP24XX_ST_MCSPI1_SHIFT 17 195#define OMAP24XX_ST_MCSPI1_MASK (1 << 17) 196#define OMAP24XX_ST_GPT12_SHIFT 14 197#define OMAP24XX_ST_GPT12_MASK (1 << 14) 198#define OMAP24XX_ST_GPT11_SHIFT 13 199#define OMAP24XX_ST_GPT11_MASK (1 << 13) 200#define OMAP24XX_ST_GPT10_SHIFT 12 201#define OMAP24XX_ST_GPT10_MASK (1 << 12) 202#define OMAP24XX_ST_GPT9_SHIFT 11 203#define OMAP24XX_ST_GPT9_MASK (1 << 11) 204#define OMAP24XX_ST_GPT8_SHIFT 10 205#define OMAP24XX_ST_GPT8_MASK (1 << 10) 206#define OMAP24XX_ST_GPT7_SHIFT 9 207#define OMAP24XX_ST_GPT7_MASK (1 << 9) 208#define OMAP24XX_ST_GPT6_SHIFT 8 209#define OMAP24XX_ST_GPT6_MASK (1 << 8) 210#define OMAP24XX_ST_GPT5_SHIFT 7 211#define OMAP24XX_ST_GPT5_MASK (1 << 7) 212#define OMAP24XX_ST_GPT4_SHIFT 6 213#define OMAP24XX_ST_GPT4_MASK (1 << 6) 214#define OMAP24XX_ST_GPT3_SHIFT 5 215#define OMAP24XX_ST_GPT3_MASK (1 << 5) 216#define OMAP24XX_ST_GPT2_SHIFT 4 217#define OMAP24XX_ST_GPT2_MASK (1 << 4) 218#define OMAP2420_ST_VLYNQ_SHIFT 3 219#define OMAP2420_ST_VLYNQ_MASK (1 << 3) 220 221/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ 222#define OMAP2430_ST_MDM_INTC_SHIFT 11 223#define OMAP2430_ST_MDM_INTC_MASK (1 << 11) 224#define OMAP2430_ST_GPIO5_SHIFT 10 225#define OMAP2430_ST_GPIO5_MASK (1 << 10) 226#define OMAP2430_ST_MCSPI3_SHIFT 9 227#define OMAP2430_ST_MCSPI3_MASK (1 << 9) 228#define OMAP2430_ST_MMCHS2_SHIFT 8 229#define OMAP2430_ST_MMCHS2_MASK (1 << 8) 230#define OMAP2430_ST_MMCHS1_SHIFT 7 231#define OMAP2430_ST_MMCHS1_MASK (1 << 7) 232#define OMAP2430_ST_USBHS_SHIFT 6 233#define OMAP2430_ST_USBHS_MASK (1 << 6) 234#define OMAP24XX_ST_UART3_SHIFT 2 235#define OMAP24XX_ST_UART3_MASK (1 << 2) 236#define OMAP24XX_ST_USB_SHIFT 0 237#define OMAP24XX_ST_USB_MASK (1 << 0) 238 239/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 240#define OMAP24XX_EN_GPIOS_SHIFT 2 241#define OMAP24XX_EN_GPIOS_MASK (1 << 2) 242#define OMAP24XX_EN_GPT1_SHIFT 0 243#define OMAP24XX_EN_GPT1_MASK (1 << 0) 244 245/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ 246#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2) 247#define OMAP24XX_ST_GPIOS_MASK 2 248#define OMAP24XX_ST_GPT1_SHIFT (1 << 0) 249#define OMAP24XX_ST_GPT1_MASK 0 250 251/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ 252#define OMAP2430_ST_MDM_SHIFT (1 << 0) 253 254 255/* 3430 register bits shared between CM & PRM registers */ 256 257/* CM_REVISION, PRM_REVISION shared bits */ 258#define OMAP3430_REV_SHIFT 0 259#define OMAP3430_REV_MASK (0xff << 0) 260 261/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ 262#define OMAP3430_AUTOIDLE_MASK (1 << 0) 263 264/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 265#define OMAP3430_EN_MMC2_MASK (1 << 25) 266#define OMAP3430_EN_MMC2_SHIFT 25 267#define OMAP3430_EN_MMC1_MASK (1 << 24) 268#define OMAP3430_EN_MMC1_SHIFT 24 269#define OMAP3430_EN_MCSPI4_MASK (1 << 21) 270#define OMAP3430_EN_MCSPI4_SHIFT 21 271#define OMAP3430_EN_MCSPI3_MASK (1 << 20) 272#define OMAP3430_EN_MCSPI3_SHIFT 20 273#define OMAP3430_EN_MCSPI2_MASK (1 << 19) 274#define OMAP3430_EN_MCSPI2_SHIFT 19 275#define OMAP3430_EN_MCSPI1_MASK (1 << 18) 276#define OMAP3430_EN_MCSPI1_SHIFT 18 277#define OMAP3430_EN_I2C3_MASK (1 << 17) 278#define OMAP3430_EN_I2C3_SHIFT 17 279#define OMAP3430_EN_I2C2_MASK (1 << 16) 280#define OMAP3430_EN_I2C2_SHIFT 16 281#define OMAP3430_EN_I2C1_MASK (1 << 15) 282#define OMAP3430_EN_I2C1_SHIFT 15 283#define OMAP3430_EN_UART2_MASK (1 << 14) 284#define OMAP3430_EN_UART2_SHIFT 14 285#define OMAP3430_EN_UART1_MASK (1 << 13) 286#define OMAP3430_EN_UART1_SHIFT 13 287#define OMAP3430_EN_GPT11_MASK (1 << 12) 288#define OMAP3430_EN_GPT11_SHIFT 12 289#define OMAP3430_EN_GPT10_MASK (1 << 11) 290#define OMAP3430_EN_GPT10_SHIFT 11 291#define OMAP3430_EN_MCBSP5_MASK (1 << 10) 292#define OMAP3430_EN_MCBSP5_SHIFT 10 293#define OMAP3430_EN_MCBSP1_MASK (1 << 9) 294#define OMAP3430_EN_MCBSP1_SHIFT 9 295#define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5) 296#define OMAP3430_EN_FSHOSTUSB_SHIFT 5 297#define OMAP3430_EN_D2D_MASK (1 << 3) 298#define OMAP3430_EN_D2D_SHIFT 3 299 300/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 301#define OMAP3430_EN_HSOTGUSB_MASK (1 << 4) 302#define OMAP3430_EN_HSOTGUSB_SHIFT 4 303 304/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ 305#define OMAP3430_ST_MMC2_SHIFT 25 306#define OMAP3430_ST_MMC2_MASK (1 << 25) 307#define OMAP3430_ST_MMC1_SHIFT 24 308#define OMAP3430_ST_MMC1_MASK (1 << 24) 309#define OMAP3430_ST_MCSPI4_SHIFT 21 310#define OMAP3430_ST_MCSPI4_MASK (1 << 21) 311#define OMAP3430_ST_MCSPI3_SHIFT 20 312#define OMAP3430_ST_MCSPI3_MASK (1 << 20) 313#define OMAP3430_ST_MCSPI2_SHIFT 19 314#define OMAP3430_ST_MCSPI2_MASK (1 << 19) 315#define OMAP3430_ST_MCSPI1_SHIFT 18 316#define OMAP3430_ST_MCSPI1_MASK (1 << 18) 317#define OMAP3430_ST_I2C3_SHIFT 17 318#define OMAP3430_ST_I2C3_MASK (1 << 17) 319#define OMAP3430_ST_I2C2_SHIFT 16 320#define OMAP3430_ST_I2C2_MASK (1 << 16) 321#define OMAP3430_ST_I2C1_SHIFT 15 322#define OMAP3430_ST_I2C1_MASK (1 << 15) 323#define OMAP3430_ST_UART2_SHIFT 14 324#define OMAP3430_ST_UART2_MASK (1 << 14) 325#define OMAP3430_ST_UART1_SHIFT 13 326#define OMAP3430_ST_UART1_MASK (1 << 13) 327#define OMAP3430_ST_GPT11_SHIFT 12 328#define OMAP3430_ST_GPT11_MASK (1 << 12) 329#define OMAP3430_ST_GPT10_SHIFT 11 330#define OMAP3430_ST_GPT10_MASK (1 << 11) 331#define OMAP3430_ST_MCBSP5_SHIFT 10 332#define OMAP3430_ST_MCBSP5_MASK (1 << 10) 333#define OMAP3430_ST_MCBSP1_SHIFT 9 334#define OMAP3430_ST_MCBSP1_MASK (1 << 9) 335#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5 336#define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5) 337#define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4 338#define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4) 339#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 340#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5) 341#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4 342#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4) 343#define OMAP3430_ST_D2D_SHIFT 3 344#define OMAP3430_ST_D2D_MASK (1 << 3) 345 346/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 347#define OMAP3430_EN_GPIO1_MASK (1 << 3) 348#define OMAP3430_EN_GPIO1_SHIFT 3 349#define OMAP3430_EN_GPT12_MASK (1 << 1) 350#define OMAP3430_EN_GPT12_SHIFT 1 351#define OMAP3430_EN_GPT1_MASK (1 << 0) 352#define OMAP3430_EN_GPT1_SHIFT 0 353 354/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ 355#define OMAP3430_EN_SR2_MASK (1 << 7) 356#define OMAP3430_EN_SR2_SHIFT 7 357#define OMAP3430_EN_SR1_MASK (1 << 6) 358#define OMAP3430_EN_SR1_SHIFT 6 359 360/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 361#define OMAP3430_EN_GPT12_MASK (1 << 1) 362#define OMAP3430_EN_GPT12_SHIFT 1 363 364/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ 365#define OMAP3430_ST_SR2_SHIFT 7 366#define OMAP3430_ST_SR2_MASK (1 << 7) 367#define OMAP3430_ST_SR1_SHIFT 6 368#define OMAP3430_ST_SR1_MASK (1 << 6) 369#define OMAP3430_ST_GPIO1_SHIFT 3 370#define OMAP3430_ST_GPIO1_MASK (1 << 3) 371#define OMAP3430_ST_GPT12_SHIFT 1 372#define OMAP3430_ST_GPT12_MASK (1 << 1) 373#define OMAP3430_ST_GPT1_SHIFT 0 374#define OMAP3430_ST_GPT1_MASK (1 << 0) 375 376/* 377 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, 378 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, 379 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits 380 */ 381#define OMAP3430_EN_MPU_MASK (1 << 1) 382#define OMAP3430_EN_MPU_SHIFT 1 383 384/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ 385#define OMAP3430_EN_GPIO6_MASK (1 << 17) 386#define OMAP3430_EN_GPIO6_SHIFT 17 387#define OMAP3430_EN_GPIO5_MASK (1 << 16) 388#define OMAP3430_EN_GPIO5_SHIFT 16 389#define OMAP3430_EN_GPIO4_MASK (1 << 15) 390#define OMAP3430_EN_GPIO4_SHIFT 15 391#define OMAP3430_EN_GPIO3_MASK (1 << 14) 392#define OMAP3430_EN_GPIO3_SHIFT 14 393#define OMAP3430_EN_GPIO2_MASK (1 << 13) 394#define OMAP3430_EN_GPIO2_SHIFT 13 395#define OMAP3430_EN_UART3_MASK (1 << 11) 396#define OMAP3430_EN_UART3_SHIFT 11 397#define OMAP3430_EN_GPT9_MASK (1 << 10) 398#define OMAP3430_EN_GPT9_SHIFT 10 399#define OMAP3430_EN_GPT8_MASK (1 << 9) 400#define OMAP3430_EN_GPT8_SHIFT 9 401#define OMAP3430_EN_GPT7_MASK (1 << 8) 402#define OMAP3430_EN_GPT7_SHIFT 8 403#define OMAP3430_EN_GPT6_MASK (1 << 7) 404#define OMAP3430_EN_GPT6_SHIFT 7 405#define OMAP3430_EN_GPT5_MASK (1 << 6) 406#define OMAP3430_EN_GPT5_SHIFT 6 407#define OMAP3430_EN_GPT4_MASK (1 << 5) 408#define OMAP3430_EN_GPT4_SHIFT 5 409#define OMAP3430_EN_GPT3_MASK (1 << 4) 410#define OMAP3430_EN_GPT3_SHIFT 4 411#define OMAP3430_EN_GPT2_MASK (1 << 3) 412#define OMAP3430_EN_GPT2_SHIFT 3 413 414/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ 415#define OMAP3430_EN_MCBSP4_MASK (1 << 2) 416#define OMAP3430_EN_MCBSP4_SHIFT 2 417#define OMAP3430_EN_MCBSP3_MASK (1 << 1) 418#define OMAP3430_EN_MCBSP3_SHIFT 1 419#define OMAP3430_EN_MCBSP2_MASK (1 << 0) 420#define OMAP3430_EN_MCBSP2_SHIFT 0 421 422/* CM_IDLEST_PER, PM_WKST_PER shared bits */ 423#define OMAP3430_ST_GPIO6_SHIFT 17 424#define OMAP3430_ST_GPIO6_MASK (1 << 17) 425#define OMAP3430_ST_GPIO5_SHIFT 16 426#define OMAP3430_ST_GPIO5_MASK (1 << 16) 427#define OMAP3430_ST_GPIO4_SHIFT 15 428#define OMAP3430_ST_GPIO4_MASK (1 << 15) 429#define OMAP3430_ST_GPIO3_SHIFT 14 430#define OMAP3430_ST_GPIO3_MASK (1 << 14) 431#define OMAP3430_ST_GPIO2_SHIFT 13 432#define OMAP3430_ST_GPIO2_MASK (1 << 13) 433#define OMAP3430_ST_UART3_SHIFT 11 434#define OMAP3430_ST_UART3_MASK (1 << 11) 435#define OMAP3430_ST_GPT9_SHIFT 10 436#define OMAP3430_ST_GPT9_MASK (1 << 10) 437#define OMAP3430_ST_GPT8_SHIFT 9 438#define OMAP3430_ST_GPT8_MASK (1 << 9) 439#define OMAP3430_ST_GPT7_SHIFT 8 440#define OMAP3430_ST_GPT7_MASK (1 << 8) 441#define OMAP3430_ST_GPT6_SHIFT 7 442#define OMAP3430_ST_GPT6_MASK (1 << 7) 443#define OMAP3430_ST_GPT5_SHIFT 6 444#define OMAP3430_ST_GPT5_MASK (1 << 6) 445#define OMAP3430_ST_GPT4_SHIFT 5 446#define OMAP3430_ST_GPT4_MASK (1 << 5) 447#define OMAP3430_ST_GPT3_SHIFT 4 448#define OMAP3430_ST_GPT3_MASK (1 << 4) 449#define OMAP3430_ST_GPT2_SHIFT 3 450#define OMAP3430_ST_GPT2_MASK (1 << 3) 451 452/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ 453#define OMAP3430_EN_CORE_SHIFT 0 454#define OMAP3430_EN_CORE_MASK (1 << 0) 455 456#endif 457