Searched refs:OMAP3430_IVA2_MOD (Results 1 - 20 of 20) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-omap2/
H A Dprcm.c300 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
302 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
326 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
327 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
364 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
368 cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
432 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
453 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
455 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
479 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
[all...]
H A Dpm34xx.c692 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
695 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
703 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
707 OMAP3430_IVA2_MOD, CM_FCLKEN);
714 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
717 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
723 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
752 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
871 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
H A Dpowerdomains34xx.h43 .prcm_offs = OMAP3430_IVA2_MOD,
232 .prcm_offs = OMAP3430_IVA2_MOD,
H A Dpm-debug.c141 { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
155 { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
H A Dprcm-common.h43 #define OMAP3430_IVA2_MOD -0x800 macro
H A Dclock3xxx_data.c347 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
353 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
360 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
362 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
395 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1122 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1132 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
H A Dclockdomains.h618 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-omap2/
H A Dprcm.c300 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
302 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
326 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
327 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
364 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
368 cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
432 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
453 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
455 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
479 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
[all...]
H A Dpm34xx.c692 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
695 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
703 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
707 OMAP3430_IVA2_MOD, CM_FCLKEN);
714 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
717 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
723 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
752 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
871 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
H A Dpowerdomains34xx.h43 .prcm_offs = OMAP3430_IVA2_MOD,
232 .prcm_offs = OMAP3430_IVA2_MOD,
H A Dpm-debug.c141 { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
155 { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
H A Dprcm-common.h43 #define OMAP3430_IVA2_MOD -0x800 macro
H A Dclock3xxx_data.c347 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
353 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
360 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
362 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
395 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1122 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1132 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
H A Dclockdomains.h618 .clkstctrl_reg = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/staging/tidspbridge/core/
H A Dtiomap3430.c270 temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
276 PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
279 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
282 while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
287 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
290 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
415 OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
433 OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
436 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
528 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PL
[all...]
H A Dtiomap3430_pwr.c89 pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
97 pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD,
198 pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
207 pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD,
H A Dtiomap_io.c422 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
433 OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/tidspbridge/core/
H A Dtiomap3430.c270 temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
276 PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
279 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
282 while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
287 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
290 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
415 OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
433 OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
436 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
528 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PL
[all...]
H A Dtiomap3430_pwr.c89 pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
97 pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD,
198 pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
207 pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD,
H A Dtiomap_io.c422 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
433 OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);

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