Searched refs:IDE_CS (Results 1 - 18 of 18) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s3c2410/
H A Dbast-ide.c37 #define IDE_CS S3C2410_CS5 macro
41 .start = IDE_CS + BAST_PA_IDEPRI,
42 .end = IDE_CS + BAST_PA_IDEPRI + (8 * 0x20) - 1,
46 .start = IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20) ,
47 .end = IDE_CS + BAST_PA_IDEPRIAUX + (7 * 0x20) - 1,
71 .start = IDE_CS + BAST_PA_IDESEC,
72 .end = IDE_CS + BAST_PA_IDESEC + (8 * 0x20) - 1,
76 .start = IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20),
77 .end = IDE_CS + BAST_PA_IDESECAUX + (7 * 0x20) - 1,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s3c2410/
H A Dbast-ide.c37 #define IDE_CS S3C2410_CS5 macro
41 .start = IDE_CS + BAST_PA_IDEPRI,
42 .end = IDE_CS + BAST_PA_IDEPRI + (8 * 0x20) - 1,
46 .start = IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20) ,
47 .end = IDE_CS + BAST_PA_IDEPRIAUX + (7 * 0x20) - 1,
71 .start = IDE_CS + BAST_PA_IDESEC,
72 .end = IDE_CS + BAST_PA_IDESEC + (8 * 0x20) - 1,
76 .start = IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20),
77 .end = IDE_CS + BAST_PA_IDESECAUX + (7 * 0x20) - 1,
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/sibyte/
H A Dbigsur.h35 #define IDE_CS 4 macro
H A Dcarmel.h47 #define IDE_CS 6 macro
H A Dswarm.h51 #define IDE_CS 4 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/sibyte/
H A Dbigsur.h35 #define IDE_CS 4 macro
H A Dcarmel.h47 #define IDE_CS 6 macro
H A Dswarm.h51 #define IDE_CS 4 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/sibyte/swarm/
H A Dplatform.c60 offset = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_START_ADDR, IDE_CS));
61 size = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_MULT_SIZE, IDE_CS));
72 pr_info(DRV_NAME ": PATA interface at GenBus slot %i\n", IDE_CS);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/sibyte/swarm/
H A Dplatform.c60 offset = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_START_ADDR, IDE_CS));
61 size = __raw_readq(base + R_IO_EXT_REG(R_IO_EXT_MULT_SIZE, IDE_CS));
72 pr_info(DRV_NAME ": PATA interface at GenBus slot %i\n", IDE_CS);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/build/broadcom/tiny/
H A Dtiny.h172 #define IDE_CS 4 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/cswarm/include/
H A Dcswarm.h172 #define IDE_CS 4 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/littlesur/include/
H A Dlittlesur.h178 #define IDE_CS 4 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/swarm/include/
H A Dswarm.h172 #define IDE_CS 4 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm1250cpci/include/
H A Dbcm1250cpci.h181 #define IDE_CS 4 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/carmel/include/
H A Dcarmel.h273 #define IDE_CS 6 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm1250cpci/src/
H A Dbcm1250cpci_init.S166 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(IDE_CS))
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/carmel/src/
H A Dcarmel_init.S211 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(IDE_CS))

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