Searched refs:IDESC (Results 1 - 25 of 186) sorted by relevance

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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/sh64/
H A Ddecode-compact.h27 extern const IDESC *sh64_compact_decode (SIM_CPU *, IADDR,
130 extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
131 extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
132 extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
133 extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
134 extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
135 extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
136 extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
137 extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
138 extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, in
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H A Ddecode-media.h27 extern const IDESC *sh64_media_decode (SIM_CPU *, IADDR,
119 extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
120 extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
121 extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
122 extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
123 extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
124 extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
125 extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
126 extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
127 extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, in
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/sh64/
H A Ddecode-compact.h27 extern const IDESC *sh64_compact_decode (SIM_CPU *, IADDR,
130 extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
131 extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
132 extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
133 extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
134 extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
135 extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
136 extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
137 extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
138 extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, in
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H A Ddecode-media.h27 extern const IDESC *sh64_media_decode (SIM_CPU *, IADDR,
119 extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
120 extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
121 extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
122 extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
123 extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
124 extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
125 extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
126 extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
127 extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, in
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/sh64/
H A Ddecode-compact.h27 extern const IDESC *sh64_compact_decode (SIM_CPU *, IADDR,
130 extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
131 extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
132 extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
133 extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
134 extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
135 extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
136 extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
137 extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
138 extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, in
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H A Ddecode-media.h27 extern const IDESC *sh64_media_decode (SIM_CPU *, IADDR,
119 extern int sh64_model_sh5_u_ftrv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvn*/);
120 extern int sh64_model_sh5_u_fipr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*fvm*/, INT /*fvn*/);
121 extern int sh64_model_sh5_u_ocb (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
122 extern int sh64_model_sh5_u_mulr_gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
123 extern int sh64_model_sh5_u_mulr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
124 extern int sh64_model_sh5_u_use_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*usereg*/);
125 extern int sh64_model_sh5_u_load_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
126 extern int sh64_model_sh5_u_set_dr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*loadreg*/);
127 extern int sh64_model_sh5_u_fcnv (SIM_CPU *, const IDESC *, in
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/frv/
H A Ddecode.h27 extern const IDESC *frvbf_decode (SIM_CPU *, IADDR,
298 extern int frvbf_model_frv_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
299 extern int frvbf_model_fr550_u_media_4_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintieven*/, INT /*FRintjeven*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
300 extern int frvbf_model_fr550_u_media_4_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
301 extern int frvbf_model_fr550_u_media_4_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
302 extern int frvbf_model_fr550_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
303 extern int frvbf_model_fr550_u_media_4_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
304 extern int frvbf_model_fr550_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
305 extern int frvbf_model_fr550_u_media_set (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/);
306 extern int frvbf_model_fr550_u_media_3_mclracc (SIM_CPU *, const IDESC *, in
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H A Dprofile-fr450.c34 frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
41 frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
52 frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
78 frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
105 frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
116 frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
127 frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
137 frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
147 frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
180 frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *ides
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H A Dcpuall.h49 const IDESC *idesc;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/frv/
H A Ddecode.h27 extern const IDESC *frvbf_decode (SIM_CPU *, IADDR,
298 extern int frvbf_model_frv_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
299 extern int frvbf_model_fr550_u_media_4_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintieven*/, INT /*FRintjeven*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
300 extern int frvbf_model_fr550_u_media_4_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
301 extern int frvbf_model_fr550_u_media_4_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
302 extern int frvbf_model_fr550_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
303 extern int frvbf_model_fr550_u_media_4_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
304 extern int frvbf_model_fr550_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
305 extern int frvbf_model_fr550_u_media_set (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/);
306 extern int frvbf_model_fr550_u_media_3_mclracc (SIM_CPU *, const IDESC *, in
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H A Dprofile-fr450.c34 frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
41 frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
52 frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
78 frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
105 frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
116 frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
127 frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
137 frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
147 frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
180 frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *ides
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/frv/
H A Ddecode.h27 extern const IDESC *frvbf_decode (SIM_CPU *, IADDR,
298 extern int frvbf_model_frv_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
299 extern int frvbf_model_fr550_u_media_4_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintieven*/, INT /*FRintjeven*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
300 extern int frvbf_model_fr550_u_media_4_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
301 extern int frvbf_model_fr550_u_media_4_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
302 extern int frvbf_model_fr550_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
303 extern int frvbf_model_fr550_u_media_4_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
304 extern int frvbf_model_fr550_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
305 extern int frvbf_model_fr550_u_media_set (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/);
306 extern int frvbf_model_fr550_u_media_3_mclracc (SIM_CPU *, const IDESC *, in
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H A Dprofile-fr450.c34 frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
41 frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
52 frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
78 frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
105 frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
116 frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
127 frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
137 frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
147 frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
180 frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *ides
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/iq2000/
H A Dcpuall.h50 const IDESC *idesc;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/iq2000/
H A Dcpuall.h50 const IDESC *idesc;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/iq2000/
H A Dcpuall.h50 const IDESC *idesc;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/m32r/
H A Ddecode.h27 extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR,
87 extern int m32rbf_model_m32r_d_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
88 extern int m32rbf_model_m32r_d_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
89 extern int m32rbf_model_m32r_d_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
90 extern int m32rbf_model_m32r_d_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
91 extern int m32rbf_model_m32r_d_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
92 extern int m32rbf_model_m32r_d_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
93 extern int m32rbf_model_test_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
H A Dcpuall.h59 const IDESC *idesc;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/m32r/
H A Ddecode.h27 extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR,
87 extern int m32rbf_model_m32r_d_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
88 extern int m32rbf_model_m32r_d_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
89 extern int m32rbf_model_m32r_d_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
90 extern int m32rbf_model_m32r_d_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
91 extern int m32rbf_model_m32r_d_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
92 extern int m32rbf_model_m32r_d_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
93 extern int m32rbf_model_test_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/m32r/
H A Ddecode.h27 extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR,
87 extern int m32rbf_model_m32r_d_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
88 extern int m32rbf_model_m32r_d_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
89 extern int m32rbf_model_m32r_d_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
90 extern int m32rbf_model_m32r_d_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
91 extern int m32rbf_model_m32r_d_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
92 extern int m32rbf_model_m32r_d_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
93 extern int m32rbf_model_test_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/cris/
H A Ddecodev32.h27 extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
126 extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Pd*/);
127 extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
128 extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/);
129 extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
130 extern int crisv32f_model_crisv32_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
131 extern int crisv32f_model_crisv32_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
132 extern int crisv32f_model_crisv32_u_jump (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Pd*/);
133 extern int crisv32f_model_crisv32_u_jump_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Ps*/);
134 extern int crisv32f_model_crisv32_u_jump_r (SIM_CPU *, const IDESC *, in
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H A Dcpuall.h72 const IDESC *idesc;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/cris/
H A Ddecodev32.h27 extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
126 extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Pd*/);
127 extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
128 extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/);
129 extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
130 extern int crisv32f_model_crisv32_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
131 extern int crisv32f_model_crisv32_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
132 extern int crisv32f_model_crisv32_u_jump (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Pd*/);
133 extern int crisv32f_model_crisv32_u_jump_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Ps*/);
134 extern int crisv32f_model_crisv32_u_jump_r (SIM_CPU *, const IDESC *, in
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H A Dcpuall.h72 const IDESC *idesc;
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/cris/
H A Ddecodev32.h27 extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR,
126 extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Pd*/);
127 extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/);
128 extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/);
129 extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
130 extern int crisv32f_model_crisv32_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
131 extern int crisv32f_model_crisv32_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
132 extern int crisv32f_model_crisv32_u_jump (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Pd*/);
133 extern int crisv32f_model_crisv32_u_jump_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Ps*/);
134 extern int crisv32f_model_crisv32_u_jump_r (SIM_CPU *, const IDESC *, in
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