Lines Matching refs:IDESC
34 frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
41 frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
52 frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
78 frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
105 frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
116 frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
127 frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
137 frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
147 frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
180 frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
191 frvbf_model_fr450_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
202 frvbf_model_fr450_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
213 frvbf_model_fr450_u_swap (SIM_CPU *cpu, const IDESC *idesc,
223 frvbf_model_fr450_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
244 frvbf_model_fr450_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
254 frvbf_model_fr450_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
264 frvbf_model_fr450_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
274 frvbf_model_fr450_u_media_1 (SIM_CPU *cpu, const IDESC *idesc,
285 frvbf_model_fr450_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc,
296 frvbf_model_fr450_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc,
306 frvbf_model_fr450_u_media_2 (SIM_CPU *cpu, const IDESC *idesc,
318 frvbf_model_fr450_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc,
330 frvbf_model_fr450_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc,
340 frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
351 frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc,
362 frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc,
373 frvbf_model_fr450_u_media_3 (SIM_CPU *cpu, const IDESC *idesc,
384 frvbf_model_fr450_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc,
394 frvbf_model_fr450_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc,
405 frvbf_model_fr450_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
417 frvbf_model_fr450_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc,
430 frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
441 frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc,
478 frvbf_model_fr450_u_media_6 (SIM_CPU *cpu, const IDESC *idesc,
488 frvbf_model_fr450_u_media_7 (SIM_CPU *cpu, const IDESC *idesc,
499 frvbf_model_fr450_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
510 frvbf_model_fr450_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
521 frvbf_model_fr450_u_ici (SIM_CPU *cpu, const IDESC *idesc,
531 frvbf_model_fr450_u_dci (SIM_CPU *cpu, const IDESC *idesc,
541 frvbf_model_fr450_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
551 frvbf_model_fr450_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
561 frvbf_model_fr450_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
571 frvbf_model_fr450_u_icul (SIM_CPU *cpu, const IDESC *idesc,
581 frvbf_model_fr450_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
591 frvbf_model_fr450_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
599 frvbf_model_fr450_u_membar (SIM_CPU *cpu, const IDESC *idesc,