1/* Decode header for m32rbf.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6
7This file is part of the GNU simulators.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 3 of the License, or
12(at your option) any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this program.  If not, see <http://www.gnu.org/licenses/>.
21
22*/
23
24#ifndef M32RBF_DECODE_H
25#define M32RBF_DECODE_H
26
27extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR,
28                                  CGEN_INSN_INT, CGEN_INSN_INT,
29                                  ARGBUF *);
30extern void m32rbf_init_idesc_table (SIM_CPU *);
31extern void m32rbf_sem_init_idesc_table (SIM_CPU *);
32extern void m32rbf_semf_init_idesc_table (SIM_CPU *);
33
34/* Enum declaration for instructions in cpu family m32rbf.  */
35typedef enum m32rbf_insn_type {
36  M32RBF_INSN_X_INVALID, M32RBF_INSN_X_AFTER, M32RBF_INSN_X_BEFORE, M32RBF_INSN_X_CTI_CHAIN
37 , M32RBF_INSN_X_CHAIN, M32RBF_INSN_X_BEGIN, M32RBF_INSN_ADD, M32RBF_INSN_ADD3
38 , M32RBF_INSN_AND, M32RBF_INSN_AND3, M32RBF_INSN_OR, M32RBF_INSN_OR3
39 , M32RBF_INSN_XOR, M32RBF_INSN_XOR3, M32RBF_INSN_ADDI, M32RBF_INSN_ADDV
40 , M32RBF_INSN_ADDV3, M32RBF_INSN_ADDX, M32RBF_INSN_BC8, M32RBF_INSN_BC24
41 , M32RBF_INSN_BEQ, M32RBF_INSN_BEQZ, M32RBF_INSN_BGEZ, M32RBF_INSN_BGTZ
42 , M32RBF_INSN_BLEZ, M32RBF_INSN_BLTZ, M32RBF_INSN_BNEZ, M32RBF_INSN_BL8
43 , M32RBF_INSN_BL24, M32RBF_INSN_BNC8, M32RBF_INSN_BNC24, M32RBF_INSN_BNE
44 , M32RBF_INSN_BRA8, M32RBF_INSN_BRA24, M32RBF_INSN_CMP, M32RBF_INSN_CMPI
45 , M32RBF_INSN_CMPU, M32RBF_INSN_CMPUI, M32RBF_INSN_DIV, M32RBF_INSN_DIVU
46 , M32RBF_INSN_REM, M32RBF_INSN_REMU, M32RBF_INSN_JL, M32RBF_INSN_JMP
47 , M32RBF_INSN_LD, M32RBF_INSN_LD_D, M32RBF_INSN_LDB, M32RBF_INSN_LDB_D
48 , M32RBF_INSN_LDH, M32RBF_INSN_LDH_D, M32RBF_INSN_LDUB, M32RBF_INSN_LDUB_D
49 , M32RBF_INSN_LDUH, M32RBF_INSN_LDUH_D, M32RBF_INSN_LD_PLUS, M32RBF_INSN_LD24
50 , M32RBF_INSN_LDI8, M32RBF_INSN_LDI16, M32RBF_INSN_LOCK, M32RBF_INSN_MACHI
51 , M32RBF_INSN_MACLO, M32RBF_INSN_MACWHI, M32RBF_INSN_MACWLO, M32RBF_INSN_MUL
52 , M32RBF_INSN_MULHI, M32RBF_INSN_MULLO, M32RBF_INSN_MULWHI, M32RBF_INSN_MULWLO
53 , M32RBF_INSN_MV, M32RBF_INSN_MVFACHI, M32RBF_INSN_MVFACLO, M32RBF_INSN_MVFACMI
54 , M32RBF_INSN_MVFC, M32RBF_INSN_MVTACHI, M32RBF_INSN_MVTACLO, M32RBF_INSN_MVTC
55 , M32RBF_INSN_NEG, M32RBF_INSN_NOP, M32RBF_INSN_NOT, M32RBF_INSN_RAC
56 , M32RBF_INSN_RACH, M32RBF_INSN_RTE, M32RBF_INSN_SETH, M32RBF_INSN_SLL
57 , M32RBF_INSN_SLL3, M32RBF_INSN_SLLI, M32RBF_INSN_SRA, M32RBF_INSN_SRA3
58 , M32RBF_INSN_SRAI, M32RBF_INSN_SRL, M32RBF_INSN_SRL3, M32RBF_INSN_SRLI
59 , M32RBF_INSN_ST, M32RBF_INSN_ST_D, M32RBF_INSN_STB, M32RBF_INSN_STB_D
60 , M32RBF_INSN_STH, M32RBF_INSN_STH_D, M32RBF_INSN_ST_PLUS, M32RBF_INSN_ST_MINUS
61 , M32RBF_INSN_SUB, M32RBF_INSN_SUBV, M32RBF_INSN_SUBX, M32RBF_INSN_TRAP
62 , M32RBF_INSN_UNLOCK, M32RBF_INSN_CLRPSW, M32RBF_INSN_SETPSW, M32RBF_INSN_BSET
63 , M32RBF_INSN_BCLR, M32RBF_INSN_BTST, M32RBF_INSN__MAX
64} M32RBF_INSN_TYPE;
65
66/* Enum declaration for semantic formats in cpu family m32rbf.  */
67typedef enum m32rbf_sfmt_type {
68  M32RBF_SFMT_EMPTY, M32RBF_SFMT_ADD, M32RBF_SFMT_ADD3, M32RBF_SFMT_AND3
69 , M32RBF_SFMT_OR3, M32RBF_SFMT_ADDI, M32RBF_SFMT_ADDV, M32RBF_SFMT_ADDV3
70 , M32RBF_SFMT_ADDX, M32RBF_SFMT_BC8, M32RBF_SFMT_BC24, M32RBF_SFMT_BEQ
71 , M32RBF_SFMT_BEQZ, M32RBF_SFMT_BL8, M32RBF_SFMT_BL24, M32RBF_SFMT_BRA8
72 , M32RBF_SFMT_BRA24, M32RBF_SFMT_CMP, M32RBF_SFMT_CMPI, M32RBF_SFMT_DIV
73 , M32RBF_SFMT_JL, M32RBF_SFMT_JMP, M32RBF_SFMT_LD, M32RBF_SFMT_LD_D
74 , M32RBF_SFMT_LDB, M32RBF_SFMT_LDB_D, M32RBF_SFMT_LDH, M32RBF_SFMT_LDH_D
75 , M32RBF_SFMT_LD_PLUS, M32RBF_SFMT_LD24, M32RBF_SFMT_LDI8, M32RBF_SFMT_LDI16
76 , M32RBF_SFMT_LOCK, M32RBF_SFMT_MACHI, M32RBF_SFMT_MULHI, M32RBF_SFMT_MV
77 , M32RBF_SFMT_MVFACHI, M32RBF_SFMT_MVFC, M32RBF_SFMT_MVTACHI, M32RBF_SFMT_MVTC
78 , M32RBF_SFMT_NOP, M32RBF_SFMT_RAC, M32RBF_SFMT_RTE, M32RBF_SFMT_SETH
79 , M32RBF_SFMT_SLL3, M32RBF_SFMT_SLLI, M32RBF_SFMT_ST, M32RBF_SFMT_ST_D
80 , M32RBF_SFMT_STB, M32RBF_SFMT_STB_D, M32RBF_SFMT_STH, M32RBF_SFMT_STH_D
81 , M32RBF_SFMT_ST_PLUS, M32RBF_SFMT_TRAP, M32RBF_SFMT_UNLOCK, M32RBF_SFMT_CLRPSW
82 , M32RBF_SFMT_SETPSW, M32RBF_SFMT_BSET, M32RBF_SFMT_BTST
83} M32RBF_SFMT_TYPE;
84
85/* Function unit handlers (user written).  */
86
87extern int m32rbf_model_m32r_d_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
88extern int m32rbf_model_m32r_d_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
89extern int m32rbf_model_m32r_d_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
90extern int m32rbf_model_m32r_d_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
91extern int m32rbf_model_m32r_d_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
92extern int m32rbf_model_m32r_d_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/, INT /*dr*/);
93extern int m32rbf_model_test_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
94
95/* Profiling before/after handlers (user written) */
96
97extern void m32rbf_model_insn_before (SIM_CPU *, int /*first_p*/);
98extern void m32rbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
99
100#endif /* M32RBF_DECODE_H */
101