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H A D | cdefBF532.h | 257 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 258 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
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H A D | defBF532.h | 264 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/ |
H A D | cdefBF532.h | 257 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 258 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
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H A D | defBF532.h | 264 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf518/include/mach/ |
H A D | cdefBF51x_base.h | 535 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 536 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
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H A D | defBF51x_base.h | 301 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf527/include/mach/ |
H A D | cdefBF52x_base.h | 552 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 553 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
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H A D | defBF52x_base.h | 301 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/ |
H A D | cdefBF51x_base.h | 535 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 536 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
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H A D | defBF51x_base.h | 301 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/ |
H A D | cdefBF52x_base.h | 552 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 553 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
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H A D | defBF52x_base.h | 301 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf537/include/mach/ |
H A D | defBF534.h | 279 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
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H A D | cdefBF534.h | 513 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 514 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/ |
H A D | defBF534.h | 279 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
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H A D | cdefBF534.h | 513 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 514 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf538/include/mach/ |
H A D | cdefBF538.h | 634 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 635 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
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H A D | defBF539.h | 284 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/ |
H A D | cdefBF538.h | 634 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 635 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
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H A D | defBF539.h | 284 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf548/include/mach/ |
H A D | defBF54x_base.h | 291 #define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */ macro
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H A D | cdefBF54x_base.h | 466 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 467 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/ |
H A D | defBF54x_base.h | 291 #define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */ macro
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H A D | cdefBF54x_base.h | 466 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT) 467 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
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