Searched refs:DMA5_Y_COUNT (Results 1 - 24 of 24) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h257 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
258 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
H A DdefBF532.h264 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h257 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
258 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
H A DdefBF532.h264 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h535 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
536 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
H A DdefBF51x_base.h301 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h552 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
553 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
H A DdefBF52x_base.h301 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h535 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
536 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
H A DdefBF51x_base.h301 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h552 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
553 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
H A DdefBF52x_base.h301 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h279 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
H A DcdefBF534.h513 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
514 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h279 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
H A DcdefBF534.h513 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
514 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT,val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h634 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
635 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
H A DdefBF539.h284 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h634 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
635 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
H A DdefBF539.h284 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h291 #define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */ macro
H A DcdefBF54x_base.h466 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
467 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h291 #define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */ macro
H A DcdefBF54x_base.h466 #define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
467 #define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)

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