Searched refs:DMA4_START_ADDR (Results 1 - 24 of 24) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h226 #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
227 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
H A DdefBF532.h248 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf533/include/mach/
H A DcdefBF532.h226 #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
227 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
H A DdefBF532.h248 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h504 #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
505 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
H A DdefBF51x_base.h283 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h521 #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
522 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
H A DdefBF52x_base.h283 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf518/include/mach/
H A DcdefBF51x_base.h504 #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
505 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
H A DdefBF51x_base.h283 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf527/include/mach/
H A DcdefBF52x_base.h521 #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
522 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
H A DdefBF52x_base.h283 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h261 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ macro
H A DcdefBF534.h482 #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
483 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf537/include/mach/
H A DdefBF534.h261 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ macro
H A DcdefBF534.h482 #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
483 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR,val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h600 #define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
601 #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
H A DdefBF539.h266 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h600 #define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
601 #define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
H A DdefBF539.h266 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h271 #define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */ macro
H A DcdefBF54x_base.h429 #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
430 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h271 #define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */ macro
H A DcdefBF54x_base.h429 #define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
430 #define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)

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