Searched refs:DMA1_RESET_REG (Results 1 - 24 of 24) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/x86/kernel/
H A Di8237.c31 dma_outb(0, DMA1_RESET_REG);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/x86/kernel/
H A Di8237.c31 dma_outb(0, DMA1_RESET_REG);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/parisc/include/asm/
H A Ddma.h57 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/alpha/kernel/
H A Dsys_sx164.c39 outb(0, DMA1_RESET_REG);
H A Dirq_alpha.c101 outb(0, DMA1_RESET_REG);
H A Dsys_eiger.c142 outb(0, DMA1_RESET_REG);
H A Dsys_dp264.c288 outb(0, DMA1_RESET_REG);
305 outb(0, DMA1_RESET_REG);
H A Dsys_titan.c236 outb(0, DMA1_RESET_REG);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/parisc/include/asm/
H A Ddma.h57 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/alpha/kernel/
H A Dsys_sx164.c39 outb(0, DMA1_RESET_REG);
H A Dirq_alpha.c101 outb(0, DMA1_RESET_REG);
H A Dsys_eiger.c142 outb(0, DMA1_RESET_REG);
H A Dsys_dp264.c288 outb(0, DMA1_RESET_REG);
305 outb(0, DMA1_RESET_REG);
H A Dsys_titan.c236 outb(0, DMA1_RESET_REG);
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/x86/include/asm/
H A Ddma.h103 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/x86/include/asm/
H A Ddma.h103 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/m68k/include/asm/
H A Dapollodma.h83 #define DMA1_RESET_REG (IO_DMA1_BASE+0x0D) /* Master Clear (w) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/mips/include/asm/
H A Ddma.h108 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/m68k/include/asm/
H A Dapollodma.h83 #define DMA1_RESET_REG (IO_DMA1_BASE+0x0D) /* Master Clear (w) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/mips/include/asm/
H A Ddma.h108 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/powerpc/include/asm/
H A Ddma.h108 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/alpha/include/asm/
H A Ddma.h140 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/powerpc/include/asm/
H A Ddma.h108 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/alpha/include/asm/
H A Ddma.h140 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ macro

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