1/* 2 * linux/arch/alpha/kernel/sys_eiger.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1996, 1999 Jay A Estabrook 6 * Copyright (C) 1998, 1999 Richard Henderson 7 * Copyright (C) 1999 Iain Grant 8 * 9 * Code supporting the EIGER (EV6+TSUNAMI). 10 */ 11 12#include <linux/kernel.h> 13#include <linux/types.h> 14#include <linux/mm.h> 15#include <linux/sched.h> 16#include <linux/pci.h> 17#include <linux/init.h> 18#include <linux/bitops.h> 19 20#include <asm/ptrace.h> 21#include <asm/system.h> 22#include <asm/dma.h> 23#include <asm/irq.h> 24#include <asm/mmu_context.h> 25#include <asm/io.h> 26#include <asm/pci.h> 27#include <asm/pgtable.h> 28#include <asm/core_tsunami.h> 29#include <asm/hwrpb.h> 30#include <asm/tlbflush.h> 31 32#include "proto.h" 33#include "irq_impl.h" 34#include "pci_impl.h" 35#include "machvec_impl.h" 36 37 38/* Note that this interrupt code is identical to TAKARA. */ 39 40/* Note mask bit is true for DISABLED irqs. */ 41static unsigned long cached_irq_mask[2] = { -1, -1 }; 42 43static inline void 44eiger_update_irq_hw(unsigned long irq, unsigned long mask) 45{ 46 int regaddr; 47 48 mask = (irq >= 64 ? mask << 16 : mask >> ((irq - 16) & 0x30)); 49 regaddr = 0x510 + (((irq - 16) >> 2) & 0x0c); 50 outl(mask & 0xffff0000UL, regaddr); 51} 52 53static inline void 54eiger_enable_irq(unsigned int irq) 55{ 56 unsigned long mask; 57 mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63))); 58 eiger_update_irq_hw(irq, mask); 59} 60 61static void 62eiger_disable_irq(unsigned int irq) 63{ 64 unsigned long mask; 65 mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63)); 66 eiger_update_irq_hw(irq, mask); 67} 68 69static unsigned int 70eiger_startup_irq(unsigned int irq) 71{ 72 eiger_enable_irq(irq); 73 return 0; /* never anything pending */ 74} 75 76static void 77eiger_end_irq(unsigned int irq) 78{ 79 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 80 eiger_enable_irq(irq); 81} 82 83static struct irq_chip eiger_irq_type = { 84 .name = "EIGER", 85 .startup = eiger_startup_irq, 86 .shutdown = eiger_disable_irq, 87 .enable = eiger_enable_irq, 88 .disable = eiger_disable_irq, 89 .ack = eiger_disable_irq, 90 .end = eiger_end_irq, 91}; 92 93static void 94eiger_device_interrupt(unsigned long vector) 95{ 96 unsigned intstatus; 97 98 /* 99 * The PALcode will have passed us vectors 0x800 or 0x810, 100 * which are fairly arbitrary values and serve only to tell 101 * us whether an interrupt has come in on IRQ0 or IRQ1. If 102 * it's IRQ1 it's a PCI interrupt; if it's IRQ0, it's 103 * probably ISA, but PCI interrupts can come through IRQ0 104 * as well if the interrupt controller isn't in accelerated 105 * mode. 106 * 107 * OTOH, the accelerator thing doesn't seem to be working 108 * overly well, so what we'll do instead is try directly 109 * examining the Master Interrupt Register to see if it's a 110 * PCI interrupt, and if _not_ then we'll pass it on to the 111 * ISA handler. 112 */ 113 114 intstatus = inw(0x500) & 15; 115 if (intstatus) { 116 /* 117 * This is a PCI interrupt. Check each bit and 118 * despatch an interrupt if it's set. 119 */ 120 121 if (intstatus & 8) handle_irq(16+3); 122 if (intstatus & 4) handle_irq(16+2); 123 if (intstatus & 2) handle_irq(16+1); 124 if (intstatus & 1) handle_irq(16+0); 125 } else { 126 isa_device_interrupt(vector); 127 } 128} 129 130static void 131eiger_srm_device_interrupt(unsigned long vector) 132{ 133 int irq = (vector - 0x800) >> 4; 134 handle_irq(irq); 135} 136 137static void __init 138eiger_init_irq(void) 139{ 140 long i; 141 142 outb(0, DMA1_RESET_REG); 143 outb(0, DMA2_RESET_REG); 144 outb(DMA_MODE_CASCADE, DMA2_MODE_REG); 145 outb(0, DMA2_MASK_REG); 146 147 if (alpha_using_srm) 148 alpha_mv.device_interrupt = eiger_srm_device_interrupt; 149 150 for (i = 16; i < 128; i += 16) 151 eiger_update_irq_hw(i, -1); 152 153 init_i8259a_irqs(); 154 155 for (i = 16; i < 128; ++i) { 156 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 157 irq_desc[i].chip = &eiger_irq_type; 158 } 159} 160 161static int __init 162eiger_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 163{ 164 u8 irq_orig; 165 166 /* The SRM console has already calculated out the IRQ value's for 167 option cards. As this works lets just read in the value already 168 set and change it to a useable value by Linux. 169 170 All the IRQ values generated by the console are greater than 90, 171 so we subtract 80 because it is (90 - allocated ISA IRQ's). */ 172 173 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq_orig); 174 175 return irq_orig - 0x80; 176} 177 178static u8 __init 179eiger_swizzle(struct pci_dev *dev, u8 *pinp) 180{ 181 struct pci_controller *hose = dev->sysdata; 182 int slot, pin = *pinp; 183 int bridge_count = 0; 184 185 /* Find the number of backplane bridges. */ 186 int backplane = inw(0x502) & 0x0f; 187 188 switch (backplane) 189 { 190 case 0x00: bridge_count = 0; break; /* No bridges */ 191 case 0x01: bridge_count = 1; break; /* 1 */ 192 case 0x03: bridge_count = 2; break; /* 2 */ 193 case 0x07: bridge_count = 3; break; /* 3 */ 194 case 0x0f: bridge_count = 4; break; /* 4 */ 195 }; 196 197 slot = PCI_SLOT(dev->devfn); 198 while (dev->bus->self) { 199 /* Check for built-in bridges on hose 0. */ 200 if (hose->index == 0 201 && (PCI_SLOT(dev->bus->self->devfn) 202 > 20 - bridge_count)) { 203 slot = PCI_SLOT(dev->devfn); 204 break; 205 } 206 /* Must be a card-based bridge. */ 207 pin = pci_swizzle_interrupt_pin(dev, pin); 208 209 /* Move up the chain of bridges. */ 210 dev = dev->bus->self; 211 } 212 *pinp = pin; 213 return slot; 214} 215 216/* 217 * The System Vectors 218 */ 219 220struct alpha_machine_vector eiger_mv __initmv = { 221 .vector_name = "Eiger", 222 DO_EV6_MMU, 223 DO_DEFAULT_RTC, 224 DO_TSUNAMI_IO, 225 .machine_check = tsunami_machine_check, 226 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 227 .min_io_address = DEFAULT_IO_BASE, 228 .min_mem_address = DEFAULT_MEM_BASE, 229 .pci_dac_offset = TSUNAMI_DAC_OFFSET, 230 231 .nr_irqs = 128, 232 .device_interrupt = eiger_device_interrupt, 233 234 .init_arch = tsunami_init_arch, 235 .init_irq = eiger_init_irq, 236 .init_rtc = common_init_rtc, 237 .init_pci = common_init_pci, 238 .kill_arch = tsunami_kill_arch, 239 .pci_map_irq = eiger_map_irq, 240 .pci_swizzle = eiger_swizzle, 241}; 242ALIAS_MV(eiger) 243