1/* 2 * linux/arch/alpha/kernel/sys_dp264.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1996, 1999 Jay A Estabrook 6 * Copyright (C) 1998, 1999 Richard Henderson 7 * 8 * Modified by Christopher C. Chimelis, 2001 to 9 * add support for the addition of Shark to the 10 * Tsunami family. 11 * 12 * Code supporting the DP264 (EV6+TSUNAMI). 13 */ 14 15#include <linux/kernel.h> 16#include <linux/types.h> 17#include <linux/mm.h> 18#include <linux/sched.h> 19#include <linux/pci.h> 20#include <linux/init.h> 21#include <linux/bitops.h> 22 23#include <asm/ptrace.h> 24#include <asm/system.h> 25#include <asm/dma.h> 26#include <asm/irq.h> 27#include <asm/mmu_context.h> 28#include <asm/io.h> 29#include <asm/pgtable.h> 30#include <asm/core_tsunami.h> 31#include <asm/hwrpb.h> 32#include <asm/tlbflush.h> 33 34#include "proto.h" 35#include "irq_impl.h" 36#include "pci_impl.h" 37#include "machvec_impl.h" 38 39 40/* Note mask bit is true for ENABLED irqs. */ 41static unsigned long cached_irq_mask; 42/* dp264 boards handle at max four CPUs */ 43static unsigned long cpu_irq_affinity[4] = { 0UL, 0UL, 0UL, 0UL }; 44 45DEFINE_SPINLOCK(dp264_irq_lock); 46 47static void 48tsunami_update_irq_hw(unsigned long mask) 49{ 50 register tsunami_cchip *cchip = TSUNAMI_cchip; 51 unsigned long isa_enable = 1UL << 55; 52 register int bcpu = boot_cpuid; 53 54#ifdef CONFIG_SMP 55 volatile unsigned long *dim0, *dim1, *dim2, *dim3; 56 unsigned long mask0, mask1, mask2, mask3, dummy; 57 58 mask &= ~isa_enable; 59 mask0 = mask & cpu_irq_affinity[0]; 60 mask1 = mask & cpu_irq_affinity[1]; 61 mask2 = mask & cpu_irq_affinity[2]; 62 mask3 = mask & cpu_irq_affinity[3]; 63 64 if (bcpu == 0) mask0 |= isa_enable; 65 else if (bcpu == 1) mask1 |= isa_enable; 66 else if (bcpu == 2) mask2 |= isa_enable; 67 else mask3 |= isa_enable; 68 69 dim0 = &cchip->dim0.csr; 70 dim1 = &cchip->dim1.csr; 71 dim2 = &cchip->dim2.csr; 72 dim3 = &cchip->dim3.csr; 73 if (!cpu_possible(0)) dim0 = &dummy; 74 if (!cpu_possible(1)) dim1 = &dummy; 75 if (!cpu_possible(2)) dim2 = &dummy; 76 if (!cpu_possible(3)) dim3 = &dummy; 77 78 *dim0 = mask0; 79 *dim1 = mask1; 80 *dim2 = mask2; 81 *dim3 = mask3; 82 mb(); 83 *dim0; 84 *dim1; 85 *dim2; 86 *dim3; 87#else 88 volatile unsigned long *dimB; 89 if (bcpu == 0) dimB = &cchip->dim0.csr; 90 else if (bcpu == 1) dimB = &cchip->dim1.csr; 91 else if (bcpu == 2) dimB = &cchip->dim2.csr; 92 else dimB = &cchip->dim3.csr; 93 94 *dimB = mask | isa_enable; 95 mb(); 96 *dimB; 97#endif 98} 99 100static void 101dp264_enable_irq(unsigned int irq) 102{ 103 spin_lock(&dp264_irq_lock); 104 cached_irq_mask |= 1UL << irq; 105 tsunami_update_irq_hw(cached_irq_mask); 106 spin_unlock(&dp264_irq_lock); 107} 108 109static void 110dp264_disable_irq(unsigned int irq) 111{ 112 spin_lock(&dp264_irq_lock); 113 cached_irq_mask &= ~(1UL << irq); 114 tsunami_update_irq_hw(cached_irq_mask); 115 spin_unlock(&dp264_irq_lock); 116} 117 118static unsigned int 119dp264_startup_irq(unsigned int irq) 120{ 121 dp264_enable_irq(irq); 122 return 0; /* never anything pending */ 123} 124 125static void 126dp264_end_irq(unsigned int irq) 127{ 128 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 129 dp264_enable_irq(irq); 130} 131 132static void 133clipper_enable_irq(unsigned int irq) 134{ 135 spin_lock(&dp264_irq_lock); 136 cached_irq_mask |= 1UL << (irq - 16); 137 tsunami_update_irq_hw(cached_irq_mask); 138 spin_unlock(&dp264_irq_lock); 139} 140 141static void 142clipper_disable_irq(unsigned int irq) 143{ 144 spin_lock(&dp264_irq_lock); 145 cached_irq_mask &= ~(1UL << (irq - 16)); 146 tsunami_update_irq_hw(cached_irq_mask); 147 spin_unlock(&dp264_irq_lock); 148} 149 150static unsigned int 151clipper_startup_irq(unsigned int irq) 152{ 153 clipper_enable_irq(irq); 154 return 0; /* never anything pending */ 155} 156 157static void 158clipper_end_irq(unsigned int irq) 159{ 160 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 161 clipper_enable_irq(irq); 162} 163 164static void 165cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity) 166{ 167 int cpu; 168 169 for (cpu = 0; cpu < 4; cpu++) { 170 unsigned long aff = cpu_irq_affinity[cpu]; 171 if (cpu_isset(cpu, affinity)) 172 aff |= 1UL << irq; 173 else 174 aff &= ~(1UL << irq); 175 cpu_irq_affinity[cpu] = aff; 176 } 177} 178 179static int 180dp264_set_affinity(unsigned int irq, const struct cpumask *affinity) 181{ 182 spin_lock(&dp264_irq_lock); 183 cpu_set_irq_affinity(irq, *affinity); 184 tsunami_update_irq_hw(cached_irq_mask); 185 spin_unlock(&dp264_irq_lock); 186 187 return 0; 188} 189 190static int 191clipper_set_affinity(unsigned int irq, const struct cpumask *affinity) 192{ 193 spin_lock(&dp264_irq_lock); 194 cpu_set_irq_affinity(irq - 16, *affinity); 195 tsunami_update_irq_hw(cached_irq_mask); 196 spin_unlock(&dp264_irq_lock); 197 198 return 0; 199} 200 201static struct irq_chip dp264_irq_type = { 202 .name = "DP264", 203 .startup = dp264_startup_irq, 204 .shutdown = dp264_disable_irq, 205 .enable = dp264_enable_irq, 206 .disable = dp264_disable_irq, 207 .ack = dp264_disable_irq, 208 .end = dp264_end_irq, 209 .set_affinity = dp264_set_affinity, 210}; 211 212static struct irq_chip clipper_irq_type = { 213 .name = "CLIPPER", 214 .startup = clipper_startup_irq, 215 .shutdown = clipper_disable_irq, 216 .enable = clipper_enable_irq, 217 .disable = clipper_disable_irq, 218 .ack = clipper_disable_irq, 219 .end = clipper_end_irq, 220 .set_affinity = clipper_set_affinity, 221}; 222 223static void 224dp264_device_interrupt(unsigned long vector) 225{ 226 printk("dp264_device_interrupt: NOT IMPLEMENTED YET!!\n"); 227} 228 229static void 230dp264_srm_device_interrupt(unsigned long vector) 231{ 232 int irq; 233 234 irq = (vector - 0x800) >> 4; 235 236 /* 237 * The SRM console reports PCI interrupts with a vector calculated by: 238 * 239 * 0x900 + (0x10 * DRIR-bit) 240 * 241 * So bit 16 shows up as IRQ 32, etc. 242 * 243 * On DP264/BRICK/MONET, we adjust it down by 16 because at least 244 * that many of the low order bits of the DRIR are not used, and 245 * so we don't count them. 246 */ 247 if (irq >= 32) 248 irq -= 16; 249 250 handle_irq(irq); 251} 252 253static void 254clipper_srm_device_interrupt(unsigned long vector) 255{ 256 int irq; 257 258 irq = (vector - 0x800) >> 4; 259 260/* 261 * The SRM console reports PCI interrupts with a vector calculated by: 262 * 263 * 0x900 + (0x10 * DRIR-bit) 264 * 265 * So bit 16 shows up as IRQ 32, etc. 266 * 267 * CLIPPER uses bits 8-47 for PCI interrupts, so we do not need 268 * to scale down the vector reported, we just use it. 269 * 270 * Eg IRQ 24 is DRIR bit 8, etc, etc 271 */ 272 handle_irq(irq); 273} 274 275static void __init 276init_tsunami_irqs(struct irq_chip * ops, int imin, int imax) 277{ 278 long i; 279 for (i = imin; i <= imax; ++i) { 280 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 281 irq_desc[i].chip = ops; 282 } 283} 284 285static void __init 286dp264_init_irq(void) 287{ 288 outb(0, DMA1_RESET_REG); 289 outb(0, DMA2_RESET_REG); 290 outb(DMA_MODE_CASCADE, DMA2_MODE_REG); 291 outb(0, DMA2_MASK_REG); 292 293 if (alpha_using_srm) 294 alpha_mv.device_interrupt = dp264_srm_device_interrupt; 295 296 tsunami_update_irq_hw(0); 297 298 init_i8259a_irqs(); 299 init_tsunami_irqs(&dp264_irq_type, 16, 47); 300} 301 302static void __init 303clipper_init_irq(void) 304{ 305 outb(0, DMA1_RESET_REG); 306 outb(0, DMA2_RESET_REG); 307 outb(DMA_MODE_CASCADE, DMA2_MODE_REG); 308 outb(0, DMA2_MASK_REG); 309 310 if (alpha_using_srm) 311 alpha_mv.device_interrupt = clipper_srm_device_interrupt; 312 313 tsunami_update_irq_hw(0); 314 315 init_i8259a_irqs(); 316 init_tsunami_irqs(&clipper_irq_type, 24, 63); 317} 318 319 320/* 321 * PCI Fixup configuration. 322 * 323 * Summary @ TSUNAMI_CSR_DIM0: 324 * Bit Meaning 325 * 0-17 Unused 326 *18 Interrupt SCSI B (Adaptec 7895 builtin) 327 *19 Interrupt SCSI A (Adaptec 7895 builtin) 328 *20 Interrupt Line D from slot 2 PCI0 329 *21 Interrupt Line C from slot 2 PCI0 330 *22 Interrupt Line B from slot 2 PCI0 331 *23 Interrupt Line A from slot 2 PCI0 332 *24 Interrupt Line D from slot 1 PCI0 333 *25 Interrupt Line C from slot 1 PCI0 334 *26 Interrupt Line B from slot 1 PCI0 335 *27 Interrupt Line A from slot 1 PCI0 336 *28 Interrupt Line D from slot 0 PCI0 337 *29 Interrupt Line C from slot 0 PCI0 338 *30 Interrupt Line B from slot 0 PCI0 339 *31 Interrupt Line A from slot 0 PCI0 340 * 341 *32 Interrupt Line D from slot 3 PCI1 342 *33 Interrupt Line C from slot 3 PCI1 343 *34 Interrupt Line B from slot 3 PCI1 344 *35 Interrupt Line A from slot 3 PCI1 345 *36 Interrupt Line D from slot 2 PCI1 346 *37 Interrupt Line C from slot 2 PCI1 347 *38 Interrupt Line B from slot 2 PCI1 348 *39 Interrupt Line A from slot 2 PCI1 349 *40 Interrupt Line D from slot 1 PCI1 350 *41 Interrupt Line C from slot 1 PCI1 351 *42 Interrupt Line B from slot 1 PCI1 352 *43 Interrupt Line A from slot 1 PCI1 353 *44 Interrupt Line D from slot 0 PCI1 354 *45 Interrupt Line C from slot 0 PCI1 355 *46 Interrupt Line B from slot 0 PCI1 356 *47 Interrupt Line A from slot 0 PCI1 357 *48-52 Unused 358 *53 PCI0 NMI (from Cypress) 359 *54 PCI0 SMI INT (from Cypress) 360 *55 PCI0 ISA Interrupt (from Cypress) 361 *56-60 Unused 362 *61 PCI1 Bus Error 363 *62 PCI0 Bus Error 364 *63 Reserved 365 * 366 * IdSel 367 * 5 Cypress Bridge I/O 368 * 6 SCSI Adaptec builtin 369 * 7 64 bit PCI option slot 0 (all busses) 370 * 8 64 bit PCI option slot 1 (all busses) 371 * 9 64 bit PCI option slot 2 (all busses) 372 * 10 64 bit PCI option slot 3 (not bus 0) 373 */ 374 375static int __init 376isa_irq_fixup(struct pci_dev *dev, int irq) 377{ 378 u8 irq8; 379 380 if (irq > 0) 381 return irq; 382 383 /* This interrupt is routed via ISA bridge, so we'll 384 just have to trust whatever value the console might 385 have assigned. */ 386 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq8); 387 388 return irq8 & 0xf; 389} 390 391static int __init 392dp264_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 393{ 394 static char irq_tab[6][5] __initdata = { 395 /*INT INTA INTB INTC INTD */ 396 { -1, -1, -1, -1, -1}, /* IdSel 5 ISA Bridge */ 397 { 16+ 3, 16+ 3, 16+ 2, 16+ 2, 16+ 2}, /* IdSel 6 SCSI builtin*/ 398 { 16+15, 16+15, 16+14, 16+13, 16+12}, /* IdSel 7 slot 0 */ 399 { 16+11, 16+11, 16+10, 16+ 9, 16+ 8}, /* IdSel 8 slot 1 */ 400 { 16+ 7, 16+ 7, 16+ 6, 16+ 5, 16+ 4}, /* IdSel 9 slot 2 */ 401 { 16+ 3, 16+ 3, 16+ 2, 16+ 1, 16+ 0} /* IdSel 10 slot 3 */ 402 }; 403 const long min_idsel = 5, max_idsel = 10, irqs_per_slot = 5; 404 struct pci_controller *hose = dev->sysdata; 405 int irq = COMMON_TABLE_LOOKUP; 406 407 if (irq > 0) 408 irq += 16 * hose->index; 409 410 return isa_irq_fixup(dev, irq); 411} 412 413static int __init 414monet_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 415{ 416 static char irq_tab[13][5] __initdata = { 417 /*INT INTA INTB INTC INTD */ 418 { 45, 45, 45, 45, 45}, /* IdSel 3 21143 PCI1 */ 419 { -1, -1, -1, -1, -1}, /* IdSel 4 unused */ 420 { -1, -1, -1, -1, -1}, /* IdSel 5 unused */ 421 { 47, 47, 47, 47, 47}, /* IdSel 6 SCSI PCI1 */ 422 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */ 423 { -1, -1, -1, -1, -1}, /* IdSel 8 P2P PCI1 */ 424 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/ 425 { 24, 24, 25, 26, 27}, /* IdSel 15 slot 5 PCI2*/ 426 { 40, 40, 41, 42, 43}, /* IdSel 11 slot 1 PCI0*/ 427 { 36, 36, 37, 38, 39}, /* IdSel 12 slot 2 PCI0*/ 428 { 32, 32, 33, 34, 35}, /* IdSel 13 slot 3 PCI0*/ 429 { 28, 28, 29, 30, 31}, /* IdSel 14 slot 4 PCI2*/ 430 { 24, 24, 25, 26, 27} /* IdSel 15 slot 5 PCI2*/ 431 }; 432 const long min_idsel = 3, max_idsel = 15, irqs_per_slot = 5; 433 434 return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP); 435} 436 437static u8 __init 438monet_swizzle(struct pci_dev *dev, u8 *pinp) 439{ 440 struct pci_controller *hose = dev->sysdata; 441 int slot, pin = *pinp; 442 443 if (!dev->bus->parent) { 444 slot = PCI_SLOT(dev->devfn); 445 } 446 /* Check for the built-in bridge on hose 1. */ 447 else if (hose->index == 1 && PCI_SLOT(dev->bus->self->devfn) == 8) { 448 slot = PCI_SLOT(dev->devfn); 449 } else { 450 /* Must be a card-based bridge. */ 451 do { 452 /* Check for built-in bridge on hose 1. */ 453 if (hose->index == 1 && 454 PCI_SLOT(dev->bus->self->devfn) == 8) { 455 slot = PCI_SLOT(dev->devfn); 456 break; 457 } 458 pin = pci_swizzle_interrupt_pin(dev, pin); 459 460 /* Move up the chain of bridges. */ 461 dev = dev->bus->self; 462 /* Slot of the next bridge. */ 463 slot = PCI_SLOT(dev->devfn); 464 } while (dev->bus->self); 465 } 466 *pinp = pin; 467 return slot; 468} 469 470static int __init 471webbrick_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 472{ 473 static char irq_tab[13][5] __initdata = { 474 /*INT INTA INTB INTC INTD */ 475 { -1, -1, -1, -1, -1}, /* IdSel 7 ISA Bridge */ 476 { -1, -1, -1, -1, -1}, /* IdSel 8 unused */ 477 { 29, 29, 29, 29, 29}, /* IdSel 9 21143 #1 */ 478 { -1, -1, -1, -1, -1}, /* IdSel 10 unused */ 479 { 30, 30, 30, 30, 30}, /* IdSel 11 21143 #2 */ 480 { -1, -1, -1, -1, -1}, /* IdSel 12 unused */ 481 { -1, -1, -1, -1, -1}, /* IdSel 13 unused */ 482 { 35, 35, 34, 33, 32}, /* IdSel 14 slot 0 */ 483 { 39, 39, 38, 37, 36}, /* IdSel 15 slot 1 */ 484 { 43, 43, 42, 41, 40}, /* IdSel 16 slot 2 */ 485 { 47, 47, 46, 45, 44}, /* IdSel 17 slot 3 */ 486 }; 487 const long min_idsel = 7, max_idsel = 17, irqs_per_slot = 5; 488 489 return isa_irq_fixup(dev, COMMON_TABLE_LOOKUP); 490} 491 492static int __init 493clipper_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 494{ 495 static char irq_tab[7][5] __initdata = { 496 /*INT INTA INTB INTC INTD */ 497 { 16+ 8, 16+ 8, 16+ 9, 16+10, 16+11}, /* IdSel 1 slot 1 */ 498 { 16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 2 slot 2 */ 499 { 16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 3 slot 3 */ 500 { 16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 4 slot 4 */ 501 { 16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 5 slot 5 */ 502 { 16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 6 slot 6 */ 503 { -1, -1, -1, -1, -1} /* IdSel 7 ISA Bridge */ 504 }; 505 const long min_idsel = 1, max_idsel = 7, irqs_per_slot = 5; 506 struct pci_controller *hose = dev->sysdata; 507 int irq = COMMON_TABLE_LOOKUP; 508 509 if (irq > 0) 510 irq += 16 * hose->index; 511 512 return isa_irq_fixup(dev, irq); 513} 514 515static void __init 516dp264_init_pci(void) 517{ 518 common_init_pci(); 519 SMC669_Init(0); 520 locate_and_init_vga(NULL); 521} 522 523static void __init 524monet_init_pci(void) 525{ 526 common_init_pci(); 527 SMC669_Init(1); 528 es1888_init(); 529 locate_and_init_vga(NULL); 530} 531 532static void __init 533clipper_init_pci(void) 534{ 535 common_init_pci(); 536 locate_and_init_vga(NULL); 537} 538 539static void __init 540webbrick_init_arch(void) 541{ 542 tsunami_init_arch(); 543 544 /* Tsunami caches 4 PTEs at a time; DS10 has only 1 hose. */ 545 hose_head->sg_isa->align_entry = 4; 546 hose_head->sg_pci->align_entry = 4; 547} 548 549 550/* 551 * The System Vectors 552 */ 553 554struct alpha_machine_vector dp264_mv __initmv = { 555 .vector_name = "DP264", 556 DO_EV6_MMU, 557 DO_DEFAULT_RTC, 558 DO_TSUNAMI_IO, 559 .machine_check = tsunami_machine_check, 560 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 561 .min_io_address = DEFAULT_IO_BASE, 562 .min_mem_address = DEFAULT_MEM_BASE, 563 .pci_dac_offset = TSUNAMI_DAC_OFFSET, 564 565 .nr_irqs = 64, 566 .device_interrupt = dp264_device_interrupt, 567 568 .init_arch = tsunami_init_arch, 569 .init_irq = dp264_init_irq, 570 .init_rtc = common_init_rtc, 571 .init_pci = dp264_init_pci, 572 .kill_arch = tsunami_kill_arch, 573 .pci_map_irq = dp264_map_irq, 574 .pci_swizzle = common_swizzle, 575}; 576ALIAS_MV(dp264) 577 578struct alpha_machine_vector monet_mv __initmv = { 579 .vector_name = "Monet", 580 DO_EV6_MMU, 581 DO_DEFAULT_RTC, 582 DO_TSUNAMI_IO, 583 .machine_check = tsunami_machine_check, 584 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 585 .min_io_address = DEFAULT_IO_BASE, 586 .min_mem_address = DEFAULT_MEM_BASE, 587 .pci_dac_offset = TSUNAMI_DAC_OFFSET, 588 589 .nr_irqs = 64, 590 .device_interrupt = dp264_device_interrupt, 591 592 .init_arch = tsunami_init_arch, 593 .init_irq = dp264_init_irq, 594 .init_rtc = common_init_rtc, 595 .init_pci = monet_init_pci, 596 .kill_arch = tsunami_kill_arch, 597 .pci_map_irq = monet_map_irq, 598 .pci_swizzle = monet_swizzle, 599}; 600 601struct alpha_machine_vector webbrick_mv __initmv = { 602 .vector_name = "Webbrick", 603 DO_EV6_MMU, 604 DO_DEFAULT_RTC, 605 DO_TSUNAMI_IO, 606 .machine_check = tsunami_machine_check, 607 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 608 .min_io_address = DEFAULT_IO_BASE, 609 .min_mem_address = DEFAULT_MEM_BASE, 610 .pci_dac_offset = TSUNAMI_DAC_OFFSET, 611 612 .nr_irqs = 64, 613 .device_interrupt = dp264_device_interrupt, 614 615 .init_arch = webbrick_init_arch, 616 .init_irq = dp264_init_irq, 617 .init_rtc = common_init_rtc, 618 .init_pci = common_init_pci, 619 .kill_arch = tsunami_kill_arch, 620 .pci_map_irq = webbrick_map_irq, 621 .pci_swizzle = common_swizzle, 622}; 623 624struct alpha_machine_vector clipper_mv __initmv = { 625 .vector_name = "Clipper", 626 DO_EV6_MMU, 627 DO_DEFAULT_RTC, 628 DO_TSUNAMI_IO, 629 .machine_check = tsunami_machine_check, 630 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 631 .min_io_address = DEFAULT_IO_BASE, 632 .min_mem_address = DEFAULT_MEM_BASE, 633 .pci_dac_offset = TSUNAMI_DAC_OFFSET, 634 635 .nr_irqs = 64, 636 .device_interrupt = dp264_device_interrupt, 637 638 .init_arch = tsunami_init_arch, 639 .init_irq = clipper_init_irq, 640 .init_rtc = common_init_rtc, 641 .init_pci = clipper_init_pci, 642 .kill_arch = tsunami_kill_arch, 643 .pci_map_irq = clipper_map_irq, 644 .pci_swizzle = common_swizzle, 645}; 646 647/* Sharks strongly resemble Clipper, at least as far 648 * as interrupt routing, etc, so we're using the 649 * same functions as Clipper does 650 */ 651 652struct alpha_machine_vector shark_mv __initmv = { 653 .vector_name = "Shark", 654 DO_EV6_MMU, 655 DO_DEFAULT_RTC, 656 DO_TSUNAMI_IO, 657 .machine_check = tsunami_machine_check, 658 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 659 .min_io_address = DEFAULT_IO_BASE, 660 .min_mem_address = DEFAULT_MEM_BASE, 661 .pci_dac_offset = TSUNAMI_DAC_OFFSET, 662 663 .nr_irqs = 64, 664 .device_interrupt = dp264_device_interrupt, 665 666 .init_arch = tsunami_init_arch, 667 .init_irq = clipper_init_irq, 668 .init_rtc = common_init_rtc, 669 .init_pci = common_init_pci, 670 .kill_arch = tsunami_kill_arch, 671 .pci_map_irq = clipper_map_irq, 672 .pci_swizzle = common_swizzle, 673}; 674 675/* No alpha_mv alias for webbrick/monet/clipper, since we compile them 676 in unconditionally with DP264; setup_arch knows how to cope. */ 677