Searched refs:DAR (Results 1 - 25 of 30) sorted by relevance

12

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/include/cpu-sh2/cpu/
H A Ddma.h16 #define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 }) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/include/cpu-sh2/cpu/
H A Ddma.h16 #define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 }) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/include/asm/
H A Ddma-register.h18 #define DAR 0x04 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/include/asm/
H A Ddma-register.h18 #define DAR 0x04 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/include/linux/
H A Dsh_dma.h25 u32 dar; /* DAR / destination address */
69 #define DAR 0x04 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/dma/
H A Dtxx9dmac.h76 u64 DAR; /* Destination Address Register */ member in struct:txx9dmac_cregs
86 u32 DAR; member in struct:txx9dmac_cregs32
211 u64 DAR; member in struct:txx9dmac_hwdesc
217 u32 DAR; member in struct:txx9dmac_hwdesc32
H A Dtxx9dmac.c303 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
307 channel64_readq(dc, DAR),
315 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
319 channel32_readl(dc, DAR),
333 channel_writeq(dc, DAR, 0);
337 channel_writel(dc, DAR, 0);
439 desc->hwdesc.DAR : desc->hwdesc32.DAR;
518 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
523 (u64)desc->CHAR, desc->SAR, desc->DAR, des
[all...]
H A Ddw_dmac_regs.h24 DW_REG(DAR); /* Destination Address Register */
79 #define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
H A Dintel_mid_dma_regs.h52 #define DAR 0x08 /* Destination Address Register*/ macro
H A Ddw_dmac.c178 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
180 channel_readl(dwc, DAR),
387 return channel_readl(dwc, DAR);
424 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
426 channel_readl(dwc, DAR),
1003 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
1005 channel_readl(dwc, DAR),
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/drivers/dma/
H A Dtxx9dmac.h76 u64 DAR; /* Destination Address Register */ member in struct:txx9dmac_cregs
86 u32 DAR; member in struct:txx9dmac_cregs32
211 u64 DAR; member in struct:txx9dmac_hwdesc
217 u32 DAR; member in struct:txx9dmac_hwdesc32
H A Dtxx9dmac.c303 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
307 channel64_readq(dc, DAR),
315 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
319 channel32_readl(dc, DAR),
333 channel_writeq(dc, DAR, 0);
337 channel_writel(dc, DAR, 0);
439 desc->hwdesc.DAR : desc->hwdesc32.DAR;
518 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
523 (u64)desc->CHAR, desc->SAR, desc->DAR, des
[all...]
H A Ddw_dmac_regs.h24 DW_REG(DAR); /* Destination Address Register */
79 #define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
H A Dintel_mid_dma_regs.h52 #define DAR 0x08 /* Destination Address Register*/ macro
H A Ddw_dmac.c178 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
180 channel_readl(dwc, DAR),
387 return channel_readl(dwc, DAR);
424 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
426 channel_readl(dwc, DAR),
1003 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
1005 channel_readl(dwc, DAR),
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/include/linux/
H A Dsh_dma.h25 u32 dar; /* DAR / destination address */
69 #define DAR 0x04 macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/router/gdb/sim/ppc/
H A Dinterrupts.c192 DAR = (spreg)ea;
193 TRACE(trace_interrupts, ("data storage interrupt - cia=0x%lx DAR=0x%lx DSISR=0x%lx\n",
195 (unsigned long)DAR,
269 DAR = (spreg)ra;
271 TRACE(trace_interrupts, ("alignment interrupt - cia=0x%lx DAR=0x%lx DSISR=0x%lx\n",
273 (unsigned long)DAR,
H A Dregisters.h330 #define DAR SPREG(spr_dar) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/router/gdb/sim/ppc/
H A Dinterrupts.c192 DAR = (spreg)ea;
193 TRACE(trace_interrupts, ("data storage interrupt - cia=0x%lx DAR=0x%lx DSISR=0x%lx\n",
195 (unsigned long)DAR,
269 DAR = (spreg)ra;
271 TRACE(trace_interrupts, ("alignment interrupt - cia=0x%lx DAR=0x%lx DSISR=0x%lx\n",
273 (unsigned long)DAR,
H A Dregisters.h330 #define DAR SPREG(spr_dar) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/router/gdb/sim/ppc/
H A Dinterrupts.c192 DAR = (spreg)ea;
193 TRACE(trace_interrupts, ("data storage interrupt - cia=0x%lx DAR=0x%lx DSISR=0x%lx\n",
195 (unsigned long)DAR,
269 DAR = (spreg)ra;
271 TRACE(trace_interrupts, ("alignment interrupt - cia=0x%lx DAR=0x%lx DSISR=0x%lx\n",
273 (unsigned long)DAR,
H A Dregisters.h330 #define DAR SPREG(spr_dar) macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/sh/drivers/dma/
H A Ddma-sh.c175 * It's important that we don't accidentally write any value to SAR/DAR
185 * SAR and DAR, regardless of value, in order for cascading to work.
192 __raw_writel(chan->dar, (dma_base_addr[chan->chan] + DAR));
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/sh/drivers/dma/
H A Ddma-sh.c175 * It's important that we don't accidentally write any value to SAR/DAR
185 * SAR and DAR, regardless of value, in order for cascading to work.
192 __raw_writel(chan->dar, (dma_base_addr[chan->chan] + DAR));
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/common/
H A Dpl330.c264 DAR, enumerator in enum:dmamov_dst
554 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
1145 /* DMAMOV DAR, x->dst_addr */
1146 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);

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