Searched refs:C0_TAGLO (Results 1 - 19 of 19) sorted by relevance

/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/lzma-loader/
H A Dhead.S13 #define C0_TAGLO $28 define
105 mtc0 zero,C0_TAGLO,2 # For mips32r2 the D$ Tags are in select 2
112 mtc0 zero,C0_TAGLO
158 mtc0 zero,C0_TAGLO
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/lzma-loader/
H A Dhead.S13 #define C0_TAGLO $28 define
105 mtc0 zero,C0_TAGLO,2 # For mips32r2 the D$ Tags are in select 2
112 mtc0 zero,C0_TAGLO
158 mtc0 zero,C0_TAGLO
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/lzma-loader/
H A Dhead.S13 #define C0_TAGLO $28 define
105 mtc0 zero,C0_TAGLO,2 # For mips32r2 the D$ Tags are in select 2
112 mtc0 zero,C0_TAGLO
158 mtc0 zero,C0_TAGLO
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm7000/src/
H A Drm7000_l1cache.S98 dmtc0 zero,C0_TAGLO
110 dmtc0 zero,C0_TAGLO,2
H A Drm7000_l2cache.S97 dmtc0 zero,C0_TAGLO
109 dmtc0 zero,C0_TAGLO,2
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/bcmcore/src/
H A Dbcmcore_l1cache.S103 mtc0 zero,C0_TAGLO
170 mtc0 zero,C0_TAGLO,2 # For mips32r2 the D$ Tags are in select 2
175 r1: mtc0 zero,C0_TAGLO
268 mtc0 zero,C0_TAGLO
352 mtc0 zero,C0_TAGLO
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/src/
H A Dsb1250_l1cache.S274 dmtc0 zero,C0_TAGLO /* assume all is good. */
276 dmtc0 zero,C0_TAGLO,2
418 dmtc0 zero,C0_TAGLO
434 dmtc0 zero,C0_TAGLO,2
H A Ddiag_l2cache.S77 #define C0_DataLo C0_TAGLO
79 #define C0_TagLo C0_TAGLO
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/
H A Dsbmips.h241 #define C0_TAGLO $28 /* CP0: TagLo */ macro
275 #define C0_TAGLO 28 /* CP0: TagLo */ macro
521 _cp0_get_reg_u64 (taglo_i, C0_TAGLO, 0)
522 _cp0_set_reg_u64 (taglo_i, C0_TAGLO, 0)
525 _cp0_get_reg_u64 (datalo_i, C0_TAGLO, 1)
528 _cp0_get_reg_u64 (taglo_d, C0_TAGLO, 2)
529 _cp0_set_reg_u64 (taglo_d, C0_TAGLO, 2)
532 _cp0_get_reg_u64 (datalo_d, C0_TAGLO, 3)
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/shared/
H A Dmin_osl.c92 MTC0(C0_TAGLO, 0, 0);
104 MTC0(C0_TAGLO, 2, 0);
107 MTC0(C0_TAGLO, 0, 0);
H A Dboot.S376 mtc0 zero,C0_TAGLO,2 # For mips32r2 the D$ Tags are in select 2
382 1: mtc0 zero,C0_TAGLO
425 mtc0 zero,C0_TAGLO
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm5200/src/
H A Drm5200_l1cache.S144 mtc0 zero,C0_TAGLO
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/include/
H A Dmipsinc.h100 #define C0_TAGLO $28 macro
178 #define C0_TAGLO 28 /* CP0: TagLo */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/bcmcore/include/
H A Dsbmips.h232 #define C0_TAGLO $28 /* CP0: TagLo */ macro
261 #define C0_TAGLO 28 /* CP0: TagLo */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm5200/include/
H A Dr5kc0.h342 #define C0_TAGLO $28 macro
458 #define C0_TAGLO 28 macro
H A Dsbmips.h231 #define C0_TAGLO $28 /* CP0: TagLo */ macro
259 #define C0_TAGLO 28 /* CP0: TagLo */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm7000/include/
H A Dr5kc0.h343 #define C0_TAGLO $28 macro
459 #define C0_TAGLO 28 macro
H A Dsbmips.h231 #define C0_TAGLO $28 /* CP0: TagLo */ macro
259 #define C0_TAGLO 28 /* CP0: TagLo */ macro
/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/verif/
H A Dvapi.S408 LSAVECP0(C0_TAGLO,54)
777 SAVECP0(C0_TAGLO,54)

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