/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src/lzma-loader/ |
H A D | head.S | 13 #define C0_TAGLO $28 define 105 mtc0 zero,C0_TAGLO,2 # For mips32r2 the D$ Tags are in select 2 112 mtc0 zero,C0_TAGLO 158 mtc0 zero,C0_TAGLO
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt/lzma-loader/ |
H A D | head.S | 13 #define C0_TAGLO $28 define 105 mtc0 zero,C0_TAGLO,2 # For mips32r2 the D$ Tags are in select 2 112 mtc0 zero,C0_TAGLO 158 mtc0 zero,C0_TAGLO
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/lzma-loader/ |
H A D | head.S | 13 #define C0_TAGLO $28 define 105 mtc0 zero,C0_TAGLO,2 # For mips32r2 the D$ Tags are in select 2 112 mtc0 zero,C0_TAGLO 158 mtc0 zero,C0_TAGLO
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm7000/src/ |
H A D | rm7000_l1cache.S | 98 dmtc0 zero,C0_TAGLO 110 dmtc0 zero,C0_TAGLO,2
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H A D | rm7000_l2cache.S | 97 dmtc0 zero,C0_TAGLO 109 dmtc0 zero,C0_TAGLO,2
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/bcmcore/src/ |
H A D | bcmcore_l1cache.S | 103 mtc0 zero,C0_TAGLO 170 mtc0 zero,C0_TAGLO,2 # For mips32r2 the D$ Tags are in select 2 175 r1: mtc0 zero,C0_TAGLO 268 mtc0 zero,C0_TAGLO 352 mtc0 zero,C0_TAGLO
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/src/ |
H A D | sb1250_l1cache.S | 274 dmtc0 zero,C0_TAGLO /* assume all is good. */ 276 dmtc0 zero,C0_TAGLO,2 418 dmtc0 zero,C0_TAGLO 434 dmtc0 zero,C0_TAGLO,2
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H A D | diag_l2cache.S | 77 #define C0_DataLo C0_TAGLO 79 #define C0_TagLo C0_TAGLO
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/ |
H A D | sbmips.h | 241 #define C0_TAGLO $28 /* CP0: TagLo */ macro 275 #define C0_TAGLO 28 /* CP0: TagLo */ macro 521 _cp0_get_reg_u64 (taglo_i, C0_TAGLO, 0) 522 _cp0_set_reg_u64 (taglo_i, C0_TAGLO, 0) 525 _cp0_get_reg_u64 (datalo_i, C0_TAGLO, 1) 528 _cp0_get_reg_u64 (taglo_d, C0_TAGLO, 2) 529 _cp0_set_reg_u64 (taglo_d, C0_TAGLO, 2) 532 _cp0_get_reg_u64 (datalo_d, C0_TAGLO, 3)
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/shared/ |
H A D | min_osl.c | 92 MTC0(C0_TAGLO, 0, 0); 104 MTC0(C0_TAGLO, 2, 0); 107 MTC0(C0_TAGLO, 0, 0);
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H A D | boot.S | 376 mtc0 zero,C0_TAGLO,2 # For mips32r2 the D$ Tags are in select 2 382 1: mtc0 zero,C0_TAGLO 425 mtc0 zero,C0_TAGLO
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm5200/src/ |
H A D | rm5200_l1cache.S | 144 mtc0 zero,C0_TAGLO
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/include/ |
H A D | mipsinc.h | 100 #define C0_TAGLO $28 macro 178 #define C0_TAGLO 28 /* CP0: TagLo */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/bcmcore/include/ |
H A D | sbmips.h | 232 #define C0_TAGLO $28 /* CP0: TagLo */ macro 261 #define C0_TAGLO 28 /* CP0: TagLo */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm5200/include/ |
H A D | r5kc0.h | 342 #define C0_TAGLO $28 macro 458 #define C0_TAGLO 28 macro
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H A D | sbmips.h | 231 #define C0_TAGLO $28 /* CP0: TagLo */ macro 259 #define C0_TAGLO 28 /* CP0: TagLo */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm7000/include/ |
H A D | r5kc0.h | 343 #define C0_TAGLO $28 macro 459 #define C0_TAGLO 28 macro
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H A D | sbmips.h | 231 #define C0_TAGLO $28 /* CP0: TagLo */ macro 259 #define C0_TAGLO 28 /* CP0: TagLo */ macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/cfe/cfe/verif/ |
H A D | vapi.S | 408 LSAVECP0(C0_TAGLO,54) 777 SAVECP0(C0_TAGLO,54)
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