1/* ********************************************************************* 2 * P5064 Board Support Package 3 * 4 * L1 Cache initialization File: rm5200_l1cache.S 5 * 6 * This module contains code to initialize the L1 cache. 7 * 8 * Note: all the routines in this module rely on registers only, 9 * since DRAM may not be active yet. 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions 27 * as they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. The "Broadcom Corporation" 31 * name may not be used to endorse or promote products derived 32 * from this software without the prior written permission of 33 * Broadcom Corporation. 34 * 35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 39 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 43 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 44 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 45 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 46 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 47 * THE POSSIBILITY OF SUCH DAMAGE. 48 ********************************************************************* */ 49 50#include "sbmips.h" 51#include "r5kc0.h" 52 53 .text 54 55 56/* ********************************************************************* 57 * Macros 58 ********************************************************************* */ 59 60#define L1CACHE_NUMWAYS 4 61#define L1CACHE_NUMIDX 256 62#define L1CACHE_LINESIZE 32 63#define L1CACHE_IDXHIGH (L1CACHE_LINESIZE*L1CACHE_NUMWAYS*L1CACHE_NUMIDX) 64 65#define L1CACHEOP(cachename,op) ((cachename) | ((op) << 2)) 66 67#define L1C_OP_IDXINVAL 0 68#define L1C_OP_IDXLOADTAG 1 69#define L1C_OP_IDXSTORETAG 2 70#define L1C_OP_IMPLRSVD 3 71#define L1C_OP_HITINVAL 4 72#define L1C_OP_FILL 5 73#define L1C_OP_HITWRITEBACK 6 74#define L1C_OP_FETCHLOCK 7 75 76#define L1C_I 0 77#define L1C_D 1 78 79#define LINESIZE 32 80#define icachesize t2 81#define dcachesize t3 82 83/* ********************************************************************* 84 * RM5200_L1CACHE_INIT() 85 * 86 * Initialize the L1 Cache tags to be "invalid" 87 * 88 * Input parameters: 89 * nothing 90 * 91 * Return value: 92 * nothing 93 * 94 * Registers used: 95 * t0,t1,t2,t3 96 ********************************************************************* */ 97 98 99#define FILLBASE 0x9fc00000 /* was K0BASE */ 100 101LEAF(rm5200_l1cache_init) 102 103 /* 104 * Determine the cache sizes 105 */ 106 107 mfc0 t0,C0_CONFIG 108 109 /* work out primary i-cache size */ 110 111 and t1,t0,CFG_ICMASK 112 srl t1,CFG_ICSHIFT 113 li icachesize,0x1000 114 sll icachesize,t1 115 116 /* work out primary d-cache size */ 117 118 and t1,t0,CFG_DCMASK 119 srl t1,CFG_DCSHIFT 120 li dcachesize,0x1000 121 sll dcachesize,t1 122 123 /* 124 * The caches may be in an indeterminate state, 125 * so we force good parity into them by doing an 126 * invalidate, load/fill, invalidate for each line. 127 */ 128 129 /* disable all i/u and cache exceptions */ 130 131 mfc0 v0,C0_SR 132 li a0,~SR_IE 133 and a0,v0 134 or a0,SR_DE 135 136 .set noreorder 137 mtc0 a0,C0_SR 138 nop 139 140 /* disable secondary cache and set zero tag */ 141 142 mfc0 t0,C0_CONFIG 143 nop 144 mtc0 zero,C0_TAGLO 145 and t0,~CFG_SE 146 mtc0 t0,C0_CONFIG 147 nop; nop; nop; nop 148 .set reorder 149 150 /* 151 * Assume bottom of ROM will generate good parity for the 152 * primary caches (max 32K) 153 */ 154 155 /* 156 * Initialise primary instruction cache. 157 */ 158 159 .set noreorder 160 li a0,FILLBASE 161 addu a1,a0,icachesize # limit = base + icachesize 1621: addu a0,LINESIZE 163 cache Index_Store_Tag_I,-4(a0) # clear tag 164 nop 165 cache Fill_I,-4(a0) # fill data line 166 nop 167 bne a0,a1,1b 168 cache Index_Store_Tag_I,-4(a0) # BDSLOT: clear tag 169 .set reorder 170 171 /* 172 * Initialise primary data cache. 173 * (for 2-way set caches, we do it in 3 passes). 174 */ 175 176 /* 1: initialise dcache tags */ 177 .set noreorder 178 li a0,FILLBASE 179 addu a1,a0,dcachesize # limit = base + dcachesize 1801: addu a0,LINESIZE 181 bne a0,a1,1b 182 cache Index_Store_Tag_D,-4(a0) # BDSLOT: clear tag 183 .set reorder 184 185 /* 2: fill dcache data */ 186 .set noreorder 187 li a0,FILLBASE 188 addu a1,a0,dcachesize # limit = base + dcachesize 1891: addu a0,LINESIZE 190 bne a0,a1,1b 191 lw zero,-4(a0) # BDSLOT: fill line 192 .set reorder 193 194 /* 3: clear dcache tags */ 195 .set noreorder 196 li a0,FILLBASE 197 addu a1,a0,dcachesize # limit = base + dcachesize 1981: addu a0,LINESIZE 199 bne a0,a1,1b 200 cache Index_Store_Tag_D,-4(a0) # BDSLOT: clear tag 201 .set reorder 202 203 mtc0 v0,C0_SR 204 j ra 205 206 207 208END(rm5200_l1cache_init) 209 210 211/* ********************************************************************* 212 * RM5200_L1CACHE_INVAL_I() 213 * 214 * Invalidate the L1 ICache 215 * 216 * Input parameters: 217 * nothing 218 * 219 * Return value: 220 * nothing 221 * 222 * Registers used: 223 * t0,t1,t2,t3 224 ********************************************************************* */ 225 226 227LEAF(rm5200_l1cache_inval_i) 228 229 /* 230 * Determine the ICache size 231 */ 232 233 mfc0 t0,C0_CONFIG 234 235 and t1,t0,CFG_ICMASK 236 srl t1,CFG_ICSHIFT 237 li icachesize,0x1000 /* t2 */ 238 sll icachesize,t1 239 240 /* 241 * Invalidate primary instruction cache. 242 */ 243 244 li t0,FILLBASE 245 addu t1,t0,icachesize # limit = base + icachesize 2461: cache L1CACHEOP(L1C_I,L1C_OP_IDXINVAL),0(t0) 247 addu t0,LINESIZE 248 bne t0,t1,1b 249 250 j ra 251 252END(rm5200_l1cache_inval_i) 253 254 255/* ********************************************************************* 256 * RM5200_L1CACHE_FLUSH_D() 257 * 258 * Flush the entire L1 DCache (write dirty lines back to memory) 259 * 260 * Input parameters: 261 * nothing 262 * 263 * Return value: 264 * nothing 265 * 266 * Registers used: 267 * t0,t1,t2,t3 268 ********************************************************************* */ 269 270 271LEAF(rm5200_l1cache_flush_d) 272 273 /* 274 * Determine the DCache size 275 */ 276 277 mfc0 t0,C0_CONFIG 278 279 and t1,t0,CFG_DCMASK 280 srl t1,CFG_DCSHIFT 281 li dcachesize,0x1000 /* t3 */ 282 sll dcachesize,t1 283 284 /* 285 * Flush data cache 286 */ 287 288 li t0,FILLBASE 289 addu t1,t0,dcachesize # limit = base + icachesize 2901: cache L1CACHEOP(L1C_D,L1C_OP_IDXINVAL),0(t0) 291 addu t0,LINESIZE 292 bne t0,t1,1b 293 294 j ra 295 296 297END(rm5200_l1cache_flush_d) 298 299 300/* ********************************************************************* 301 * End 302 ********************************************************************* */ 303