1/* ********************************************************************* 2 * RM7000 Board Support Package 3 * 4 * L1 Cache initialization File: rm7000_l1cache.S 5 * 6 * This module contains code to initialize the L1 cache. 7 * 8 * Note: all the routines in this module rely on registers only, 9 * since DRAM may not be active yet. 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This software is furnished under license and may be used and 19 * copied only in accordance with the following terms and 20 * conditions. Subject to these conditions, you may download, 21 * copy, install, use, modify and distribute modified or unmodified 22 * copies of this software in source and/or binary form. No title 23 * or ownership is transferred hereby. 24 * 25 * 1) Any source code used, modified or distributed must reproduce 26 * and retain this copyright notice and list of conditions 27 * as they appear in the source file. 28 * 29 * 2) No right is granted to use any trade name, trademark, or 30 * logo of Broadcom Corporation. The "Broadcom Corporation" 31 * name may not be used to endorse or promote products derived 32 * from this software without the prior written permission of 33 * Broadcom Corporation. 34 * 35 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 36 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 37 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 38 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 39 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 40 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 41 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 42 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 43 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 44 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 45 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 46 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 47 * THE POSSIBILITY OF SUCH DAMAGE. 48 ********************************************************************* */ 49 50#include "sbmips.h" 51 52 .text 53 54 55/* ********************************************************************* 56 * Macros 57 ********************************************************************* */ 58 59#define L1CACHE_NUMWAYS 4 60#define L1CACHE_NUMIDX 128 /* RM7000 has only 16K */ 61#define L1CACHE_LINESIZE 32 62#define L1CACHE_IDXHIGH (L1CACHE_LINESIZE*L1CACHE_NUMWAYS*L1CACHE_NUMIDX) 63 64#define L1CACHEOP(cachename,op) ((cachename) | ((op) << 2)) 65 66#define L1C_OP_IDXINVAL 0 67#define L1C_OP_IDXLOADTAG 1 68#define L1C_OP_IDXSTORETAG 2 69#define L1C_OP_IMPLRSVD 3 70#define L1C_OP_HITINVAL 4 71#define L1C_OP_FILL 5 72#define L1C_OP_HITWRITEBACK 6 73#define L1C_OP_FETCHLOCK 7 74 75#define L1C_I 0 76#define L1C_D 1 77 78 79 80/* ********************************************************************* 81 * RM7000_L1CACHE_INIT() 82 * 83 * Initialize the L1 Cache tags to be "invalid" 84 * 85 * Input parameters: 86 * nothing 87 * 88 * Return value: 89 * nothing 90 * 91 * Registers used: 92 * t0,t1,t2,t3 93 ********************************************************************* */ 94 95 96LEAF(rm7000_l1cache_init) 97 98 dmtc0 zero,C0_TAGLO 99 dmtc0 zero,C0_TAGHI 100 101 102 li t2,K1BASE 103 li t3,L1CACHE_IDXHIGH 104 105 add t0,t2,t3 1061: cache L1CACHEOP(L1C_I,L1C_OP_IDXSTORETAG),0(t2) 107 addu t2,L1CACHE_LINESIZE 108 bne t0,t2,1b 109 110 dmtc0 zero,C0_TAGLO,2 111 dmtc0 zero,C0_TAGHI,2 112 113 li t2,K1BASE 114 add t0,t2,t3 1151: cache L1CACHEOP(L1C_D,L1C_OP_IDXSTORETAG),0(t2) 116 addu t2,L1CACHE_LINESIZE 117 bne t0,t2,1b 118 119 j ra 120 121END(rm7000_l1cache_init) 122 123 124/* ********************************************************************* 125 * RM7000_L1CACHE_INVAL_I() 126 * 127 * Invalidate the L1 ICache 128 * 129 * Input parameters: 130 * nothing 131 * 132 * Return value: 133 * nothing 134 * 135 * Registers used: 136 * t0,t1,t2,t3 137 ********************************************************************* */ 138 139 140LEAF(rm7000_l1cache_inval_i) 141 142 143 li t2,K1BASE 144 li t3,L1CACHE_IDXHIGH 145 146 add t0,t2,t3 1471: cache L1CACHEOP(L1C_I,L1C_OP_IDXINVAL),0(t2) 148 addu t2,L1CACHE_LINESIZE 149 bne t0,t2,1b 150 151 j ra 152 153END(rm7000_l1cache_inval_i) 154 155 156/* ********************************************************************* 157 * RM7000_L1CACHE_FLUSH_D() 158 * 159 * Flush the entire L1 DCache (write dirty lines back to memory) 160 * 161 * Input parameters: 162 * nothing 163 * 164 * Return value: 165 * nothing 166 * 167 * Registers used: 168 * t0,t1,t2,t3 169 ********************************************************************* */ 170 171 172LEAF(rm7000_l1cache_flush_d) 173 174 li t2,K1BASE 175 li t3,L1CACHE_IDXHIGH 176 177 li t2,K1BASE 178 add t0,t2,t3 1791: cache L1CACHEOP(L1C_D,L1C_OP_IDXINVAL),0(t2) 180 addu t2,L1CACHE_LINESIZE 181 bne t0,t2,1b 182 183 j ra 184 185END(rm7000_l1cache_flush_d) 186 187 188/* ********************************************************************* 189 * End 190 ********************************************************************* */ 191