Searched refs:UART_CLK (Results 1 - 13 of 13) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/au1000/common/
H A Ddbg_io.c48 #define UART_CLK 0x28 /* Baud Rat4e Clock Divider */ macro
75 UART16550_WRITE(UART_CLK, divisor & 0xffff);
H A Dpower.c214 au_readl(UART_BASE + UART_CLK +
237 UART_BASE + UART_CLK +
H A Dserial.c1126 serial_outp(info, UART_CLK, quot & 0xffff);
3051 serial_out(info, UART_CLK, quot & 0xffff);
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/au1000/pb1100/
H A Dsetup.c225 au_writel(0, UART0_ADDR + UART_CLK);
227 au_writel(0, UART1_ADDR + UART_CLK);
228 au_writel(0, UART3_ADDR + UART_CLK);
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/au1000/pb1000/
H A Dsetup.c275 au_writel(0, UART0_ADDR + UART_CLK);
277 au_writel(0, UART1_ADDR + UART_CLK);
278 au_writel(0, UART2_ADDR + UART_CLK);
279 au_writel(0, UART3_ADDR + UART_CLK);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-sh/
H A Dsmc37c93x.h160 #define UART_CLK (1843200) /* 1.8432 MHz */ macro
161 #define UART_BAUD(x) (UART_CLK / (16 * (x)))
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-sh/
H A Dsmc37c93x.h160 #define UART_CLK (1843200) /* 1.8432 MHz */ macro
161 #define UART_BAUD(x) (UART_CLK / (16 * (x)))
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/au1000/pb1500/
H A Dsetup.c229 au_writel(0, UART0_ADDR + UART_CLK);
231 au_writel(0, UART3_ADDR + UART_CLK);
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/au1000/db1x00/
H A Dsetup.c191 au_writel(0, UART0_ADDR + UART_CLK);
193 //au_writel(0, UART3_ADDR + UART_CLK);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/
H A Dau1000.h596 #define UART_CLK 0x28 /* Baud Rate Clock Divider */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/
H A Dau1000.h596 #define UART_CLK 0x28 /* Baud Rate Clock Divider */ macro
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/
H A Dau1000.h596 #define UART_CLK 0x28 /* Baud Rate Clock Divider */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/
H A Dau1000.h596 #define UART_CLK 0x28 /* Baud Rate Clock Divider */ macro

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