1/* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * Include file for Alchemy Semiconductor's Au1k CPU. 5 * 6 * Copyright 2000,2001 MontaVista Software Inc. 7 * Author: MontaVista Software, Inc. 8 * ppopov@mvista.com or source@mvista.com 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * You should have received a copy of the GNU General Public License along 27 * with this program; if not, write to the Free Software Foundation, Inc., 28 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 */ 30 31 /* 32 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp 33 */ 34 35#ifndef _AU1000_H_ 36#define _AU1000_H_ 37 38#include <linux/delay.h> 39#include <asm/io.h> 40 41/* cpu pipeline flush */ 42void static inline au_sync(void) 43{ 44 __asm__ volatile ("sync"); 45} 46 47void static inline au_sync_udelay(int us) 48{ 49 __asm__ volatile ("sync"); 50 udelay(us); 51} 52 53void static inline au_sync_delay(int ms) 54{ 55 __asm__ volatile ("sync"); 56 mdelay(ms); 57} 58 59void static inline au_writeb(u8 val, int reg) 60{ 61 *(volatile u8 *)(reg) = val; 62} 63 64void static inline au_writew(u16 val, int reg) 65{ 66 *(volatile u16 *)(reg) = val; 67} 68 69void static inline au_writel(u32 val, int reg) 70{ 71 *(volatile u32 *)(reg) = val; 72} 73 74static inline u8 au_readb(unsigned long port) 75{ 76 return (*(volatile u8 *)port); 77} 78 79static inline u16 au_readw(unsigned long port) 80{ 81 return (*(volatile u16 *)port); 82} 83 84static inline u32 au_readl(unsigned long port) 85{ 86 return (*(volatile u32 *)port); 87} 88 89/* arch/mips/au1000/common/clocks.c */ 90extern void set_au1x00_speed(unsigned int new_freq); 91extern unsigned int get_au1x00_speed(void); 92extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); 93extern unsigned long get_au1x00_uart_baud_base(void); 94extern void set_au1x00_lcd_clock(void); 95extern unsigned int get_au1x00_lcd_clock(void); 96 97#ifdef CONFIG_PM 98/* no CP0 timer irq */ 99#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) 100#else 101#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) 102#endif 103 104/* SDRAM Controller */ 105#define MEM_SDMODE0 0xB4000000 106#define MEM_SDMODE1 0xB4000004 107#define MEM_SDMODE2 0xB4000008 108 109#define MEM_SDADDR0 0xB400000C 110#define MEM_SDADDR1 0xB4000010 111#define MEM_SDADDR2 0xB4000014 112 113#define MEM_SDREFCFG 0xB4000018 114#define MEM_SDPRECMD 0xB400001C 115#define MEM_SDAUTOREF 0xB4000020 116 117#define MEM_SDWRMD0 0xB4000024 118#define MEM_SDWRMD1 0xB4000028 119#define MEM_SDWRMD2 0xB400002C 120 121#define MEM_SDSLEEP 0xB4000030 122#define MEM_SDSMCKE 0xB4000034 123 124/* Static Bus Controller */ 125#define MEM_STCFG0 0xB4001000 126#define MEM_STTIME0 0xB4001004 127#define MEM_STADDR0 0xB4001008 128 129#define MEM_STCFG1 0xB4001010 130#define MEM_STTIME1 0xB4001014 131#define MEM_STADDR1 0xB4001018 132 133#define MEM_STCFG2 0xB4001020 134#define MEM_STTIME2 0xB4001024 135#define MEM_STADDR2 0xB4001028 136 137#define MEM_STCFG3 0xB4001030 138#define MEM_STTIME3 0xB4001034 139#define MEM_STADDR3 0xB4001038 140 141/* Interrupt Controller 0 */ 142#define IC0_CFG0RD 0xB0400040 143#define IC0_CFG0SET 0xB0400040 144#define IC0_CFG0CLR 0xB0400044 145 146#define IC0_CFG1RD 0xB0400048 147#define IC0_CFG1SET 0xB0400048 148#define IC0_CFG1CLR 0xB040004C 149 150#define IC0_CFG2RD 0xB0400050 151#define IC0_CFG2SET 0xB0400050 152#define IC0_CFG2CLR 0xB0400054 153 154#define IC0_REQ0INT 0xB0400054 155#define IC0_SRCRD 0xB0400058 156#define IC0_SRCSET 0xB0400058 157#define IC0_SRCCLR 0xB040005C 158#define IC0_REQ1INT 0xB040005C 159 160#define IC0_ASSIGNRD 0xB0400060 161#define IC0_ASSIGNSET 0xB0400060 162#define IC0_ASSIGNCLR 0xB0400064 163 164#define IC0_WAKERD 0xB0400068 165#define IC0_WAKESET 0xB0400068 166#define IC0_WAKECLR 0xB040006C 167 168#define IC0_MASKRD 0xB0400070 169#define IC0_MASKSET 0xB0400070 170#define IC0_MASKCLR 0xB0400074 171 172#define IC0_RISINGRD 0xB0400078 173#define IC0_RISINGCLR 0xB0400078 174#define IC0_FALLINGRD 0xB040007C 175#define IC0_FALLINGCLR 0xB040007C 176 177#define IC0_TESTBIT 0xB0400080 178 179/* Interrupt Controller 1 */ 180#define IC1_CFG0RD 0xB1800040 181#define IC1_CFG0SET 0xB1800040 182#define IC1_CFG0CLR 0xB1800044 183 184#define IC1_CFG1RD 0xB1800048 185#define IC1_CFG1SET 0xB1800048 186#define IC1_CFG1CLR 0xB180004C 187 188#define IC1_CFG2RD 0xB1800050 189#define IC1_CFG2SET 0xB1800050 190#define IC1_CFG2CLR 0xB1800054 191 192#define IC1_REQ0INT 0xB1800054 193#define IC1_SRCRD 0xB1800058 194#define IC1_SRCSET 0xB1800058 195#define IC1_SRCCLR 0xB180005C 196#define IC1_REQ1INT 0xB180005C 197 198#define IC1_ASSIGNRD 0xB1800060 199#define IC1_ASSIGNSET 0xB1800060 200#define IC1_ASSIGNCLR 0xB1800064 201 202#define IC1_WAKERD 0xB1800068 203#define IC1_WAKESET 0xB1800068 204#define IC1_WAKECLR 0xB180006C 205 206#define IC1_MASKRD 0xB1800070 207#define IC1_MASKSET 0xB1800070 208#define IC1_MASKCLR 0xB1800074 209 210#define IC1_RISINGRD 0xB1800078 211#define IC1_RISINGCLR 0xB1800078 212#define IC1_FALLINGRD 0xB180007C 213#define IC1_FALLINGCLR 0xB180007C 214 215#define IC1_TESTBIT 0xB1800080 216 217/* Interrupt Configuration Modes */ 218#define INTC_INT_DISABLED 0 219#define INTC_INT_RISE_EDGE 0x1 220#define INTC_INT_FALL_EDGE 0x2 221#define INTC_INT_RISE_AND_FALL_EDGE 0x3 222#define INTC_INT_HIGH_LEVEL 0x5 223#define INTC_INT_LOW_LEVEL 0x6 224#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7 225 226/* Interrupt Numbers */ 227#define AU1000_UART0_INT 0 228#define AU1000_UART1_INT 1 /* au1000 */ 229#define AU1000_UART2_INT 2 /* au1000 */ 230 231#define AU1000_PCI_INTA 1 /* au1500 */ 232#define AU1000_PCI_INTB 2 /* au1500 */ 233 234#define AU1000_UART3_INT 3 235 236#define AU1000_SSI0_INT 4 /* au1000 */ 237#define AU1000_SSI1_INT 5 /* au1000 */ 238 239#define AU1000_PCI_INTC 4 /* au1500 */ 240#define AU1000_PCI_INTD 5 /* au1500 */ 241 242#define AU1000_DMA_INT_BASE 6 243#define AU1000_TOY_INT 14 244#define AU1000_TOY_MATCH0_INT 15 245#define AU1000_TOY_MATCH1_INT 16 246#define AU1000_TOY_MATCH2_INT 17 247#define AU1000_RTC_INT 18 248#define AU1000_RTC_MATCH0_INT 19 249#define AU1000_RTC_MATCH1_INT 20 250#define AU1000_RTC_MATCH2_INT 21 251#define AU1000_IRDA_TX_INT 22 /* au1000 */ 252#define AU1000_IRDA_RX_INT 23 /* au1000 */ 253#define AU1000_USB_DEV_REQ_INT 24 254#define AU1000_USB_DEV_SUS_INT 25 255#define AU1000_USB_HOST_INT 26 256#define AU1000_ACSYNC_INT 27 257#define AU1000_MAC0_DMA_INT 28 258#define AU1000_MAC1_DMA_INT 29 259#define AU1000_ETH0_IRQ AU1000_MAC0_DMA_INT 260#define AU1000_ETH1_IRQ AU1000_MAC1_DMA_INT 261#define AU1000_I2S_UO_INT 30 /* au1000 */ 262#define AU1000_AC97C_INT 31 263#define AU1000_LAST_INTC0_INT AU1000_AC97C_INT 264#define AU1000_GPIO_0 32 265#define AU1000_GPIO_1 33 266#define AU1000_GPIO_2 34 267#define AU1000_GPIO_3 35 268#define AU1000_GPIO_4 36 269#define AU1000_GPIO_5 37 270#define AU1000_GPIO_6 38 271#define AU1000_GPIO_7 39 272#define AU1000_GPIO_8 40 273#define AU1000_GPIO_9 41 274#define AU1000_GPIO_10 42 275#define AU1000_GPIO_11 43 276#define AU1000_GPIO_12 44 277#define AU1000_GPIO_13 45 278#define AU1000_GPIO_14 46 279#define AU1000_GPIO_15 47 280 281/* Au1000 only */ 282#define AU1000_GPIO_16 48 283#define AU1000_GPIO_17 49 284#define AU1000_GPIO_18 50 285#define AU1000_GPIO_19 51 286#define AU1000_GPIO_20 52 287#define AU1000_GPIO_21 53 288#define AU1000_GPIO_22 54 289#define AU1000_GPIO_23 55 290#define AU1000_GPIO_24 56 291#define AU1000_GPIO_25 57 292#define AU1000_GPIO_26 58 293#define AU1000_GPIO_27 59 294#define AU1000_GPIO_28 60 295#define AU1000_GPIO_29 61 296#define AU1000_GPIO_30 62 297#define AU1000_GPIO_31 63 298 299/* Au1500 only */ 300#define AU1500_GPIO_200 48 301#define AU1500_GPIO_201 49 302#define AU1500_GPIO_202 50 303#define AU1500_GPIO_203 51 304#define AU1500_GPIO_20 52 305#define AU1500_GPIO_204 53 306#define AU1500_GPIO_205 54 307#define AU1500_GPIO_23 55 308#define AU1500_GPIO_24 56 309#define AU1500_GPIO_25 57 310#define AU1500_GPIO_26 58 311#define AU1500_GPIO_27 59 312#define AU1500_GPIO_28 60 313#define AU1500_GPIO_206 61 314#define AU1500_GPIO_207 62 315#define AU1500_GPIO_208_215 63 316 317#define AU1000_MAX_INTR 63 318 319#define AU1100_SD 2 320#define AU1100_GPIO_208_215 29 321// REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE 322 323 324 325/* Programmable Counters 0 and 1 */ 326#define SYS_BASE 0xB1900000 327#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 328 #define SYS_CNTRL_E1S (1<<23) 329 #define SYS_CNTRL_T1S (1<<20) 330 #define SYS_CNTRL_M21 (1<<19) 331 #define SYS_CNTRL_M11 (1<<18) 332 #define SYS_CNTRL_M01 (1<<17) 333 #define SYS_CNTRL_C1S (1<<16) 334 #define SYS_CNTRL_BP (1<<14) 335 #define SYS_CNTRL_EN1 (1<<13) 336 #define SYS_CNTRL_BT1 (1<<12) 337 #define SYS_CNTRL_EN0 (1<<11) 338 #define SYS_CNTRL_BT0 (1<<10) 339 #define SYS_CNTRL_E0 (1<<8) 340 #define SYS_CNTRL_E0S (1<<7) 341 #define SYS_CNTRL_32S (1<<5) 342 #define SYS_CNTRL_T0S (1<<4) 343 #define SYS_CNTRL_M20 (1<<3) 344 #define SYS_CNTRL_M10 (1<<2) 345 #define SYS_CNTRL_M00 (1<<1) 346 #define SYS_CNTRL_C0S (1<<0) 347 348/* Programmable Counter 0 Registers */ 349#define SYS_TOYTRIM (SYS_BASE + 0) 350#define SYS_TOYWRITE (SYS_BASE + 4) 351#define SYS_TOYMATCH0 (SYS_BASE + 8) 352#define SYS_TOYMATCH1 (SYS_BASE + 0xC) 353#define SYS_TOYMATCH2 (SYS_BASE + 0x10) 354#define SYS_TOYREAD (SYS_BASE + 0x40) 355 356/* Programmable Counter 1 Registers */ 357#define SYS_RTCTRIM (SYS_BASE + 0x44) 358#define SYS_RTCWRITE (SYS_BASE + 0x48) 359#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) 360#define SYS_RTCMATCH1 (SYS_BASE + 0x50) 361#define SYS_RTCMATCH2 (SYS_BASE + 0x54) 362#define SYS_RTCREAD (SYS_BASE + 0x58) 363 364/* I2S Controller */ 365#define I2S_DATA 0xB1000000 366 #define I2S_DATA_MASK (0xffffff) 367#define I2S_CONFIG 0xB1000004 368 #define I2S_CONFIG_XU (1<<25) 369 #define I2S_CONFIG_XO (1<<24) 370 #define I2S_CONFIG_RU (1<<23) 371 #define I2S_CONFIG_RO (1<<22) 372 #define I2S_CONFIG_TR (1<<21) 373 #define I2S_CONFIG_TE (1<<20) 374 #define I2S_CONFIG_TF (1<<19) 375 #define I2S_CONFIG_RR (1<<18) 376 #define I2S_CONFIG_RE (1<<17) 377 #define I2S_CONFIG_RF (1<<16) 378 #define I2S_CONFIG_PD (1<<11) 379 #define I2S_CONFIG_LB (1<<10) 380 #define I2S_CONFIG_IC (1<<9) 381 #define I2S_CONFIG_FM_BIT 7 382 #define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT) 383 #define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT) 384 #define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT) 385 #define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT) 386 #define I2S_CONFIG_TN (1<<6) 387 #define I2S_CONFIG_RN (1<<5) 388 #define I2S_CONFIG_SZ_BIT 0 389 #define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT) 390 391#define I2S_CONTROL 0xB1000008 392 #define I2S_CONTROL_D (1<<1) 393 #define I2S_CONTROL_CE (1<<0) 394 395/* USB Host Controller */ 396// We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address 397#define USB_OHCI_BASE 0x10100000 398#define USB_OHCI_LEN 0x00100000 399#define USB_HOST_CONFIG 0xB017fffc 400 401/* USB Device Controller */ 402#define USBD_EP0RD 0xB0200000 403#define USBD_EP0WR 0xB0200004 404#define USBD_EP2WR 0xB0200008 405#define USBD_EP3WR 0xB020000C 406#define USBD_EP4RD 0xB0200010 407#define USBD_EP5RD 0xB0200014 408#define USBD_INTEN 0xB0200018 409#define USBD_INTSTAT 0xB020001C 410 #define USBDEV_INT_SOF (1<<12) 411 #define USBDEV_INT_HF_BIT 6 412 #define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT) 413 #define USBDEV_INT_CMPLT_BIT 0 414 #define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT) 415#define USBD_CONFIG 0xB0200020 416#define USBD_EP0CS 0xB0200024 417#define USBD_EP2CS 0xB0200028 418#define USBD_EP3CS 0xB020002C 419#define USBD_EP4CS 0xB0200030 420#define USBD_EP5CS 0xB0200034 421 #define USBDEV_CS_SU (1<<14) 422 #define USBDEV_CS_NAK (1<<13) 423 #define USBDEV_CS_ACK (1<<12) 424 #define USBDEV_CS_BUSY (1<<11) 425 #define USBDEV_CS_TSIZE_BIT 1 426 #define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT) 427 #define USBDEV_CS_STALL (1<<0) 428#define USBD_EP0RDSTAT 0xB0200040 429#define USBD_EP0WRSTAT 0xB0200044 430#define USBD_EP2WRSTAT 0xB0200048 431#define USBD_EP3WRSTAT 0xB020004C 432#define USBD_EP4RDSTAT 0xB0200050 433#define USBD_EP5RDSTAT 0xB0200054 434 #define USBDEV_FSTAT_FLUSH (1<<6) 435 #define USBDEV_FSTAT_UF (1<<5) 436 #define USBDEV_FSTAT_OF (1<<4) 437 #define USBDEV_FSTAT_FCNT_BIT 0 438 #define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT) 439#define USBD_ENABLE 0xB0200058 440 #define USBDEV_ENABLE (1<<1) 441 #define USBDEV_CE (1<<0) 442 443/* Ethernet Controllers */ 444#define AU1000_ETH0_BASE 0xB0500000 445#define AU1000_ETH1_BASE 0xB0510000 446#define AU1500_ETH0_BASE 0xB1500000 447#define AU1500_ETH1_BASE 0xB1510000 448#define AU1100_ETH0_BASE 0xB0500000 449 450/* 4 byte offsets from AU1000_ETH_BASE */ 451#define MAC_CONTROL 0x0 452 #define MAC_RX_ENABLE (1<<2) 453 #define MAC_TX_ENABLE (1<<3) 454 #define MAC_DEF_CHECK (1<<5) 455 #define MAC_SET_BL(X) (((X)&0x3)<<6) 456 #define MAC_AUTO_PAD (1<<8) 457 #define MAC_DISABLE_RETRY (1<<10) 458 #define MAC_DISABLE_BCAST (1<<11) 459 #define MAC_LATE_COL (1<<12) 460 #define MAC_HASH_MODE (1<<13) 461 #define MAC_HASH_ONLY (1<<15) 462 #define MAC_PASS_ALL (1<<16) 463 #define MAC_INVERSE_FILTER (1<<17) 464 #define MAC_PROMISCUOUS (1<<18) 465 #define MAC_PASS_ALL_MULTI (1<<19) 466 #define MAC_FULL_DUPLEX (1<<20) 467 #define MAC_NORMAL_MODE 0 468 #define MAC_INT_LOOPBACK (1<<21) 469 #define MAC_EXT_LOOPBACK (1<<22) 470 #define MAC_DISABLE_RX_OWN (1<<23) 471 #define MAC_BIG_ENDIAN (1<<30) 472 #define MAC_RX_ALL (1<<31) 473#define MAC_ADDRESS_HIGH 0x4 474#define MAC_ADDRESS_LOW 0x8 475#define MAC_MCAST_HIGH 0xC 476#define MAC_MCAST_LOW 0x10 477#define MAC_MII_CNTRL 0x14 478 #define MAC_MII_BUSY (1<<0) 479 #define MAC_MII_READ 0 480 #define MAC_MII_WRITE (1<<1) 481 #define MAC_SET_MII_SELECT_REG(X) (((X)&0x1f)<<6) 482 #define MAC_SET_MII_SELECT_PHY(X) (((X)&0x1f)<<11) 483#define MAC_MII_DATA 0x18 484#define MAC_FLOW_CNTRL 0x1C 485 #define MAC_FLOW_CNTRL_BUSY (1<<0) 486 #define MAC_FLOW_CNTRL_ENABLE (1<<1) 487 #define MAC_PASS_CONTROL (1<<2) 488 #define MAC_SET_PAUSE(X) (((X)&0xffff)<<16) 489#define MAC_VLAN1_TAG 0x20 490#define MAC_VLAN2_TAG 0x24 491 492/* Ethernet Controller Enable */ 493#define AU1000_MAC0_ENABLE 0xB0520000 494#define AU1000_MAC1_ENABLE 0xB0520004 495#define AU1500_MAC0_ENABLE 0xB1520000 496#define AU1500_MAC1_ENABLE 0xB1520004 497#define AU1100_MAC0_ENABLE 0xB0520000 498 499 #define MAC_EN_CLOCK_ENABLE (1<<0) 500 #define MAC_EN_RESET0 (1<<1) 501 #define MAC_EN_TOSS (0<<2) 502 #define MAC_EN_CACHEABLE (1<<3) 503 #define MAC_EN_RESET1 (1<<4) 504 #define MAC_EN_RESET2 (1<<5) 505 #define MAC_DMA_RESET (1<<6) 506 507/* Ethernet Controller DMA Channels */ 508 509#define MAC0_TX_DMA_ADDR 0xB4004000 510#define MAC1_TX_DMA_ADDR 0xB4004200 511/* offsets from MAC_TX_RING_ADDR address */ 512#define MAC_TX_BUFF0_STATUS 0x0 513 #define TX_FRAME_ABORTED (1<<0) 514 #define TX_JAB_TIMEOUT (1<<1) 515 #define TX_NO_CARRIER (1<<2) 516 #define TX_LOSS_CARRIER (1<<3) 517 #define TX_EXC_DEF (1<<4) 518 #define TX_LATE_COLL_ABORT (1<<5) 519 #define TX_EXC_COLL (1<<6) 520 #define TX_UNDERRUN (1<<7) 521 #define TX_DEFERRED (1<<8) 522 #define TX_LATE_COLL (1<<9) 523 #define TX_COLL_CNT_MASK (0xF<<10) 524 #define TX_PKT_RETRY (1<<31) 525#define MAC_TX_BUFF0_ADDR 0x4 526 #define TX_DMA_ENABLE (1<<0) 527 #define TX_T_DONE (1<<1) 528 #define TX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 529#define MAC_TX_BUFF0_LEN 0x8 530#define MAC_TX_BUFF1_STATUS 0x10 531#define MAC_TX_BUFF1_ADDR 0x14 532#define MAC_TX_BUFF1_LEN 0x18 533#define MAC_TX_BUFF2_STATUS 0x20 534#define MAC_TX_BUFF2_ADDR 0x24 535#define MAC_TX_BUFF2_LEN 0x28 536#define MAC_TX_BUFF3_STATUS 0x30 537#define MAC_TX_BUFF3_ADDR 0x34 538#define MAC_TX_BUFF3_LEN 0x38 539 540#define MAC0_RX_DMA_ADDR 0xB4004100 541#define MAC1_RX_DMA_ADDR 0xB4004300 542/* offsets from MAC_RX_RING_ADDR */ 543#define MAC_RX_BUFF0_STATUS 0x0 544 #define RX_FRAME_LEN_MASK 0x3fff 545 #define RX_WDOG_TIMER (1<<14) 546 #define RX_RUNT (1<<15) 547 #define RX_OVERLEN (1<<16) 548 #define RX_COLL (1<<17) 549 #define RX_ETHER (1<<18) 550 #define RX_MII_ERROR (1<<19) 551 #define RX_DRIBBLING (1<<20) 552 #define RX_CRC_ERROR (1<<21) 553 #define RX_VLAN1 (1<<22) 554 #define RX_VLAN2 (1<<23) 555 #define RX_LEN_ERROR (1<<24) 556 #define RX_CNTRL_FRAME (1<<25) 557 #define RX_U_CNTRL_FRAME (1<<26) 558 #define RX_MCAST_FRAME (1<<27) 559 #define RX_BCAST_FRAME (1<<28) 560 #define RX_FILTER_FAIL (1<<29) 561 #define RX_PACKET_FILTER (1<<30) 562 #define RX_MISSED_FRAME (1<<31) 563 564 #define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 565 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 566 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 567#define MAC_RX_BUFF0_ADDR 0x4 568 #define RX_DMA_ENABLE (1<<0) 569 #define RX_T_DONE (1<<1) 570 #define RX_GET_DMA_BUFFER(X) (((X)>>2)&0x3) 571 #define RX_SET_BUFF_ADDR(X) ((X)&0xffffffc0) 572#define MAC_RX_BUFF1_STATUS 0x10 573#define MAC_RX_BUFF1_ADDR 0x14 574#define MAC_RX_BUFF2_STATUS 0x20 575#define MAC_RX_BUFF2_ADDR 0x24 576#define MAC_RX_BUFF3_STATUS 0x30 577#define MAC_RX_BUFF3_ADDR 0x34 578 579 580/* UARTS 0-3 */ 581#define UART_BASE 0xB1100000 582#define UART0_ADDR 0xB1100000 583#define UART1_ADDR 0xB1200000 584#define UART2_ADDR 0xB1300000 585#define UART3_ADDR 0xB1400000 586 587#define UART_RX 0 /* Receive buffer */ 588#define UART_TX 4 /* Transmit buffer */ 589#define UART_IER 8 /* Interrupt Enable Register */ 590#define UART_IIR 0xC /* Interrupt ID Register */ 591#define UART_FCR 0x10 /* FIFO Control Register */ 592#define UART_LCR 0x14 /* Line Control Register */ 593#define UART_MCR 0x18 /* Modem Control Register */ 594#define UART_LSR 0x1C /* Line Status Register */ 595#define UART_MSR 0x20 /* Modem Status Register */ 596#define UART_CLK 0x28 /* Baud Rate Clock Divider */ 597#define UART_MOD_CNTRL 0x100 /* Module Control */ 598 599#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ 600#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 601#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 602#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 603#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */ 604#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */ 605#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */ 606#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */ 607#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */ 608#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */ 609#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */ 610#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */ 611#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */ 612 613/* 614 * These are the definitions for the Line Control Register 615 */ 616#define UART_LCR_SBC 0x40 /* Set break control */ 617#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ 618#define UART_LCR_EPAR 0x10 /* Even parity select */ 619#define UART_LCR_PARITY 0x08 /* Parity Enable */ 620#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ 621#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ 622#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ 623#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ 624#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ 625 626/* 627 * These are the definitions for the Line Status Register 628 */ 629#define UART_LSR_TEMT 0x40 /* Transmitter empty */ 630#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 631#define UART_LSR_BI 0x10 /* Break interrupt indicator */ 632#define UART_LSR_FE 0x08 /* Frame error indicator */ 633#define UART_LSR_PE 0x04 /* Parity error indicator */ 634#define UART_LSR_OE 0x02 /* Overrun error indicator */ 635#define UART_LSR_DR 0x01 /* Receiver data ready */ 636 637/* 638 * These are the definitions for the Interrupt Identification Register 639 */ 640#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 641#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 642#define UART_IIR_MSI 0x00 /* Modem status interrupt */ 643#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 644#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 645#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 646 647/* 648 * These are the definitions for the Interrupt Enable Register 649 */ 650#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 651#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 652#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 653#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 654 655/* 656 * These are the definitions for the Modem Control Register 657 */ 658#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 659#define UART_MCR_OUT2 0x08 /* Out2 complement */ 660#define UART_MCR_OUT1 0x04 /* Out1 complement */ 661#define UART_MCR_RTS 0x02 /* RTS complement */ 662#define UART_MCR_DTR 0x01 /* DTR complement */ 663 664/* 665 * These are the definitions for the Modem Status Register 666 */ 667#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 668#define UART_MSR_RI 0x40 /* Ring Indicator */ 669#define UART_MSR_DSR 0x20 /* Data Set Ready */ 670#define UART_MSR_CTS 0x10 /* Clear to Send */ 671#define UART_MSR_DDCD 0x08 /* Delta DCD */ 672#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 673#define UART_MSR_DDSR 0x02 /* Delta DSR */ 674#define UART_MSR_DCTS 0x01 /* Delta CTS */ 675#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ 676 677 678 679/* SSIO */ 680#define SSI0_STATUS 0xB1600000 681 #define SSI_STATUS_BF (1<<4) 682 #define SSI_STATUS_OF (1<<3) 683 #define SSI_STATUS_UF (1<<2) 684 #define SSI_STATUS_D (1<<1) 685 #define SSI_STATUS_B (1<<0) 686#define SSI0_INT 0xB1600004 687 #define SSI_INT_OI (1<<3) 688 #define SSI_INT_UI (1<<2) 689 #define SSI_INT_DI (1<<1) 690#define SSI0_INT_ENABLE 0xB1600008 691 #define SSI_INTE_OIE (1<<3) 692 #define SSI_INTE_UIE (1<<2) 693 #define SSI_INTE_DIE (1<<1) 694#define SSI0_CONFIG 0xB1600020 695 #define SSI_CONFIG_AO (1<<24) 696 #define SSI_CONFIG_DO (1<<23) 697 #define SSI_CONFIG_ALEN_BIT 20 698 #define SSI_CONFIG_ALEN_MASK (0x7<<20) 699 #define SSI_CONFIG_DLEN_BIT 16 700 #define SSI_CONFIG_DLEN_MASK (0x7<<16) 701 #define SSI_CONFIG_DD (1<<11) 702 #define SSI_CONFIG_AD (1<<10) 703 #define SSI_CONFIG_BM_BIT 8 704 #define SSI_CONFIG_BM_MASK (0x3<<8) 705 #define SSI_CONFIG_CE (1<<7) 706 #define SSI_CONFIG_DP (1<<6) 707 #define SSI_CONFIG_DL (1<<5) 708 #define SSI_CONFIG_EP (1<<4) 709#define SSI0_ADATA 0xB1600024 710 #define SSI_AD_D (1<<24) 711 #define SSI_AD_ADDR_BIT 16 712 #define SSI_AD_ADDR_MASK (0xff<<16) 713 #define SSI_AD_DATA_BIT 0 714 #define SSI_AD_DATA_MASK (0xfff<<0) 715#define SSI0_CLKDIV 0xB1600028 716#define SSI0_CONTROL 0xB1600100 717 #define SSI_CONTROL_CD (1<<1) 718 #define SSI_CONTROL_E (1<<0) 719 720/* SSI1 */ 721#define SSI1_STATUS 0xB1680000 722#define SSI1_INT 0xB1680004 723#define SSI1_INT_ENABLE 0xB1680008 724#define SSI1_CONFIG 0xB1680020 725#define SSI1_ADATA 0xB1680024 726#define SSI1_CLKDIV 0xB1680028 727#define SSI1_ENABLE 0xB1680100 728 729/* 730 * Register content definitions 731 */ 732#define SSI_STATUS_BF (1<<4) 733#define SSI_STATUS_OF (1<<3) 734#define SSI_STATUS_UF (1<<2) 735#define SSI_STATUS_D (1<<1) 736#define SSI_STATUS_B (1<<0) 737 738/* SSI_INT */ 739#define SSI_INT_OI (1<<3) 740#define SSI_INT_UI (1<<2) 741#define SSI_INT_DI (1<<1) 742 743/* SSI_INTEN */ 744#define SSI_INTEN_OIE (1<<3) 745#define SSI_INTEN_UIE (1<<2) 746#define SSI_INTEN_DIE (1<<1) 747 748#define SSI_CONFIG_AO (1<<24) 749#define SSI_CONFIG_DO (1<<23) 750#define SSI_CONFIG_ALEN (7<<20) 751#define SSI_CONFIG_DLEN (15<<16) 752#define SSI_CONFIG_DD (1<<11) 753#define SSI_CONFIG_AD (1<<10) 754#define SSI_CONFIG_BM (3<<8) 755#define SSI_CONFIG_CE (1<<7) 756#define SSI_CONFIG_DP (1<<6) 757#define SSI_CONFIG_DL (1<<5) 758#define SSI_CONFIG_EP (1<<4) 759#define SSI_CONFIG_ALEN_N(N) ((N-1)<<20) 760#define SSI_CONFIG_DLEN_N(N) ((N-1)<<16) 761#define SSI_CONFIG_BM_HI (0<<8) 762#define SSI_CONFIG_BM_LO (1<<8) 763#define SSI_CONFIG_BM_CY (2<<8) 764 765#define SSI_ADATA_D (1<<24) 766#define SSI_ADATA_ADDR (0xFF<<16) 767#define SSI_ADATA_DATA (0x0FFF) 768#define SSI_ADATA_ADDR_N(N) (N<<16) 769 770#define SSI_ENABLE_CD (1<<1) 771#define SSI_ENABLE_E (1<<0) 772 773 774/* IrDA Controller */ 775#define IRDA_BASE 0xB0300000 776#define IR_RING_PTR_STATUS (IRDA_BASE+0x00) 777#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04) 778#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08) 779#define IR_RING_SIZE (IRDA_BASE+0x0C) 780#define IR_RING_PROMPT (IRDA_BASE+0x10) 781#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14) 782#define IR_INT_CLEAR (IRDA_BASE+0x18) 783#define IR_CONFIG_1 (IRDA_BASE+0x20) 784 #define IR_RX_INVERT_LED (1<<0) 785 #define IR_TX_INVERT_LED (1<<1) 786 #define IR_ST (1<<2) 787 #define IR_SF (1<<3) 788 #define IR_SIR (1<<4) 789 #define IR_MIR (1<<5) 790 #define IR_FIR (1<<6) 791 #define IR_16CRC (1<<7) 792 #define IR_TD (1<<8) 793 #define IR_RX_ALL (1<<9) 794 #define IR_DMA_ENABLE (1<<10) 795 #define IR_RX_ENABLE (1<<11) 796 #define IR_TX_ENABLE (1<<12) 797 #define IR_LOOPBACK (1<<14) 798 #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ 799 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) 800#define IR_SIR_FLAGS (IRDA_BASE+0x24) 801#define IR_ENABLE (IRDA_BASE+0x28) 802 #define IR_RX_STATUS (1<<9) 803 #define IR_TX_STATUS (1<<10) 804#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C) 805#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30) 806#define IR_MAX_PKT_LEN (IRDA_BASE+0x34) 807#define IR_RX_BYTE_CNT (IRDA_BASE+0x38) 808#define IR_CONFIG_2 (IRDA_BASE+0x3C) 809 #define IR_MODE_INV (1<<0) 810 #define IR_ONE_PIN (1<<1) 811#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40) 812 813/* GPIO */ 814#define SYS_PINFUNC 0xB190002C 815 #define SYS_PF_USB (1<<15) /* 2nd USB device/host */ 816 #define SYS_PF_U3 (1<<14) /* GPIO23/U3TXD */ 817 #define SYS_PF_U2 (1<<13) /* GPIO22/U2TXD */ 818 #define SYS_PF_U1 (1<<12) /* GPIO21/U1TXD */ 819 #define SYS_PF_SRC (1<<11) /* GPIO6/SROMCKE */ 820 #define SYS_PF_CK5 (1<<10) /* GPIO3/CLK5 */ 821 #define SYS_PF_CK4 (1<<9) /* GPIO2/CLK4 */ 822 #define SYS_PF_IRF (1<<8) /* GPIO15/IRFIRSEL */ 823 #define SYS_PF_UR3 (1<<7) /* GPIO[14:9]/UART3 */ 824 #define SYS_PF_I2D (1<<6) /* GPIO8/I2SDI */ 825 #define SYS_PF_I2S (1<<5) /* I2S/GPIO[29:31] */ 826 #define SYS_PF_NI2 (1<<4) /* NI2/GPIO[24:28] */ 827 #define SYS_PF_U0 (1<<3) /* U0TXD/GPIO20 */ 828 #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ 829 #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ 830 #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ 831#define SYS_TRIOUTRD 0xB1900100 832#define SYS_TRIOUTCLR 0xB1900100 833#define SYS_OUTPUTRD 0xB1900108 834#define SYS_OUTPUTSET 0xB1900108 835#define SYS_OUTPUTCLR 0xB190010C 836#define SYS_PINSTATERD 0xB1900110 837#define SYS_PININPUTEN 0xB1900110 838 839/* GPIO2, Au1500 only */ 840#define GPIO2_BASE 0xB1700000 841#define GPIO2_DIR (GPIO2_BASE + 0) 842#define GPIO2_DATA_EN (GPIO2_BASE + 8) 843#define GPIO2_PIN_STATE (GPIO2_BASE + 0xC) 844#define GPIO2_INT_MASK (GPIO2_BASE + 0x10) 845#define GPIO2_CONTROL (GPIO2_BASE + 0x14) 846 847/* Power Management */ 848#define SYS_SCRATCH0 0xB1900018 849#define SYS_SCRATCH1 0xB190001C 850#define SYS_WAKEMSK 0xB1900034 851#define SYS_ENDIAN 0xB1900038 852#define SYS_POWERCTRL 0xB190003C 853#define SYS_WAKESRC 0xB190005C 854#define SYS_SLPPWR 0xB1900078 855#define SYS_SLEEP 0xB190007C 856 857/* Clock Controller */ 858#define SYS_FREQCTRL0 0xB1900020 859 #define SYS_FC_FRDIV2_BIT 22 860 #define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT) 861 #define SYS_FC_FE2 (1<<21) 862 #define SYS_FC_FS2 (1<<20) 863 #define SYS_FC_FRDIV1_BIT 12 864 #define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT) 865 #define SYS_FC_FE1 (1<<11) 866 #define SYS_FC_FS1 (1<<10) 867 #define SYS_FC_FRDIV0_BIT 2 868 #define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT) 869 #define SYS_FC_FE0 (1<<1) 870 #define SYS_FC_FS0 (1<<0) 871#define SYS_FREQCTRL1 0xB1900024 872 #define SYS_FC_FRDIV5_BIT 22 873 #define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT) 874 #define SYS_FC_FE5 (1<<21) 875 #define SYS_FC_FS5 (1<<20) 876 #define SYS_FC_FRDIV4_BIT 12 877 #define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT) 878 #define SYS_FC_FE4 (1<<11) 879 #define SYS_FC_FS4 (1<<10) 880 #define SYS_FC_FRDIV3_BIT 2 881 #define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT) 882 #define SYS_FC_FE3 (1<<1) 883 #define SYS_FC_FS3 (1<<0) 884#define SYS_CLKSRC 0xB1900028 885 #define SYS_CS_ME1_BIT 27 886 #define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT) 887 #define SYS_CS_DE1 (1<<26) 888 #define SYS_CS_CE1 (1<<25) 889 #define SYS_CS_ME0_BIT 22 890 #define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT) 891 #define SYS_CS_DE0 (1<<21) 892 #define SYS_CS_CE0 (1<<20) 893 #define SYS_CS_MI2_BIT 17 894 #define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT) 895 #define SYS_CS_DI2 (1<<16) 896 #define SYS_CS_CI2 (1<<15) 897 #define SYS_CS_MUH_BIT 12 898 #define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT) 899 #define SYS_CS_DUH (1<<11) 900 #define SYS_CS_CUH (1<<10) 901 #define SYS_CS_MUD_BIT 7 902 #define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT) 903 #define SYS_CS_DUD (1<<6) 904 #define SYS_CS_CUD (1<<5) 905 #define SYS_CS_MIR_BIT 2 906 #define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT) 907 #define SYS_CS_DIR (1<<1) 908 #define SYS_CS_CIR (1<<0) 909 910 #define SYS_CS_MUX_AUX 0x1 911 #define SYS_CS_MUX_FQ0 0x2 912 #define SYS_CS_MUX_FQ1 0x3 913 #define SYS_CS_MUX_FQ2 0x4 914 #define SYS_CS_MUX_FQ3 0x5 915 #define SYS_CS_MUX_FQ4 0x6 916 #define SYS_CS_MUX_FQ5 0x7 917#define SYS_CPUPLL 0xB1900060 918#define SYS_AUXPLL 0xB1900064 919 920/* AC97 Controller */ 921#define AC97C_CONFIG 0xB0000000 922 #define AC97C_RECV_SLOTS_BIT 13 923 #define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT) 924 #define AC97C_XMIT_SLOTS_BIT 3 925 #define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT) 926 #define AC97C_SG (1<<2) 927 #define AC97C_SYNC (1<<1) 928 #define AC97C_RESET (1<<0) 929#define AC97C_STATUS 0xB0000004 930 #define AC97C_XU (1<<11) 931 #define AC97C_XO (1<<10) 932 #define AC97C_RU (1<<9) 933 #define AC97C_RO (1<<8) 934 #define AC97C_READY (1<<7) 935 #define AC97C_CP (1<<6) 936 #define AC97C_TR (1<<5) 937 #define AC97C_TE (1<<4) 938 #define AC97C_TF (1<<3) 939 #define AC97C_RR (1<<2) 940 #define AC97C_RE (1<<1) 941 #define AC97C_RF (1<<0) 942#define AC97C_DATA 0xB0000008 943#define AC97C_CMD 0xB000000C 944 #define AC97C_WD_BIT 16 945 #define AC97C_READ (1<<7) 946 #define AC97C_INDEX_MASK 0x7f 947#define AC97C_CNTRL 0xB0000010 948 #define AC97C_RS (1<<1) 949 #define AC97C_CE (1<<0) 950 951/* Au1500 PCI Controller */ 952#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr 953#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) 954#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4) 955 #define PCI_ERROR ((1<<22) | (1<<23) | (1<<24) | (1<<25) | (1<<26) | (1<<27)) 956#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8) 957#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC) 958#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10) 959#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14) 960#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18) 961#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C) 962#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20) 963#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100) 964#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104) 965#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108) 966#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C) 967#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110) 968 969#define Au1500_PCI_HDR 0xB4005100 // virtual, kseg0 addr 970 971/* All of our structures, like pci resource, have 32 bit members. 972 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's 973 * hard to store 0x4 0000 0000 in a 32 bit type. We require a small patch 974 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and 975 * (u32)Au1500_PCI_MEM_END and change those to the full 36 bit PCI MEM 976 * addresses. For PCI IO, it's simpler because we get to do the ioremap 977 * ourselves and then adjust the device's resources. 978 */ 979#define Au1500_EXT_CFG 0x600000000 980#define Au1500_EXT_CFG_TYPE1 0x680000000 981#define Au1500_PCI_IO_START 0x500000000 982#define Au1500_PCI_IO_END 0x5000FFFFF 983#define Au1500_PCI_MEM_START 0x440000000 984#define Au1500_PCI_MEM_END 0x443FFFFFF 985 986#endif 987