1/* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * Alchemy Pb1000 board setup. 5 * 6 * Copyright 2000 MontaVista Software Inc. 7 * Author: MontaVista Software, Inc. 8 * ppopov@mvista.com or source@mvista.com 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * You should have received a copy of the GNU General Public License along 27 * with this program; if not, write to the Free Software Foundation, Inc., 28 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 */ 30#include <linux/config.h> 31#include <linux/init.h> 32#include <linux/sched.h> 33#include <linux/ioport.h> 34#include <linux/mm.h> 35#include <linux/console.h> 36#include <linux/mc146818rtc.h> 37#include <linux/delay.h> 38 39#include <asm/cpu.h> 40#include <asm/bootinfo.h> 41#include <asm/irq.h> 42#include <asm/keyboard.h> 43#include <asm/mipsregs.h> 44#include <asm/reboot.h> 45#include <asm/pgtable.h> 46#include <asm/au1000.h> 47#include <asm/pb1000.h> 48 49#ifdef CONFIG_USB_OHCI 50// Enable the workaround for the OHCI DoneHead 51// register corruption problem. 52#define CONFIG_AU1000_OHCI_FIX 53#endif 54 55#if defined(CONFIG_AU1X00_SERIAL_CONSOLE) 56extern void console_setup(char *, int *); 57char serial_console[20]; 58#endif 59 60#ifdef CONFIG_BLK_DEV_INITRD 61extern unsigned long initrd_start, initrd_end; 62extern void * __rd_start, * __rd_end; 63#endif 64 65#ifdef CONFIG_BLK_DEV_IDE 66extern struct ide_ops std_ide_ops; 67extern struct ide_ops *ide_ops; 68#endif 69 70void (*__wbflush) (void); 71extern struct rtc_ops no_rtc_ops; 72extern char * __init prom_getcmdline(void); 73extern void au1000_restart(char *); 74extern void au1000_halt(void); 75extern void au1000_power_off(void); 76extern struct resource ioport_resource; 77extern struct resource iomem_resource; 78 79void __init bus_error_init(void) { /* nothing */ } 80 81void au1000_wbflush(void) 82{ 83 __asm__ volatile ("sync"); 84} 85 86void __init au1x00_setup(void) 87{ 88 char *argptr; 89 u32 pin_func, static_cfg0; 90 u32 sys_freqctrl, sys_clksrc; 91 u32 prid = read_c0_prid(); 92 93 argptr = prom_getcmdline(); 94 95 /* Various early Au1000 Errata corrected by this */ 96 set_c0_config(1<<19); /* Config[OD] */ 97 98#ifdef CONFIG_AU1X00_SERIAL_CONSOLE 99 if ((argptr = strstr(argptr, "console=")) == NULL) { 100 argptr = prom_getcmdline(); 101 strcat(argptr, " console=ttyS0,115200"); 102 } 103#endif 104 105 rtc_ops = &no_rtc_ops; 106 __wbflush = au1000_wbflush; 107 _machine_restart = au1000_restart; 108 _machine_halt = au1000_halt; 109 _machine_power_off = au1000_power_off; 110 111 // IO/MEM resources. 112 set_io_port_base(0); 113 ioport_resource.start = 0x10000000; 114 ioport_resource.end = 0xffffffff; 115 iomem_resource.start = 0x10000000; 116 iomem_resource.end = 0xffffffff; 117 118#ifdef CONFIG_BLK_DEV_INITRD 119 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); 120 initrd_start = (unsigned long)&__rd_start; 121 initrd_end = (unsigned long)&__rd_end; 122#endif 123 124 // set AUX clock to 12MHz * 8 = 96 MHz 125 au_writel(8, SYS_AUXPLL); 126 au_writel(0, SYS_PINSTATERD); 127 udelay(100); 128 129#if defined(CONFIG_USB_OHCI) || defined(CONFIG_AU1X00_USB_DEVICE) 130#ifdef CONFIG_USB_OHCI 131 if ((argptr = strstr(argptr, "usb_ohci=")) == NULL) { 132 char usb_args[80]; 133 argptr = prom_getcmdline(); 134 memset(usb_args, 0, sizeof(usb_args)); 135 sprintf(usb_args, " usb_ohci=base:0x%x,len:0x%x,irq:%d", 136 USB_OHCI_BASE, USB_OHCI_LEN, AU1000_USB_HOST_INT); 137 strcat(argptr, usb_args); 138 } 139#endif 140 141 /* zero and disable FREQ2 */ 142 sys_freqctrl = au_readl(SYS_FREQCTRL0); 143 sys_freqctrl &= ~0xFFF00000; 144 au_writel(sys_freqctrl, SYS_FREQCTRL0); 145 146 /* zero and disable USBH/USBD clocks */ 147 sys_clksrc = au_readl(SYS_CLKSRC); 148 sys_clksrc &= ~0x00007FE0; 149 au_writel(sys_clksrc, SYS_CLKSRC); 150 151 sys_freqctrl = au_readl(SYS_FREQCTRL0); 152 sys_freqctrl &= ~0xFFF00000; 153 154 sys_clksrc = au_readl(SYS_CLKSRC); 155 sys_clksrc &= ~0x00007FE0; 156 157 switch (prid & 0x000000FF) 158 { 159 case 0x00: /* DA */ 160 case 0x01: /* HA */ 161 case 0x02: /* HB */ 162 /* CPU core freq to 48MHz to slow it way down... */ 163 au_writel(4, SYS_CPUPLL); 164 165 /* 166 * Setup 48MHz FREQ2 from CPUPLL for USB Host 167 */ 168 /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */ 169 sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20)); 170 au_writel(sys_freqctrl, SYS_FREQCTRL0); 171 172 /* CPU core freq to 384MHz */ 173 au_writel(0x20, SYS_CPUPLL); 174 175 printk("Au1000: 48MHz OHCI workaround enabled\n"); 176 break; 177 178 default: /* HC and newer */ 179 // FREQ2 = aux/2 = 48 MHz 180 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); 181 au_writel(sys_freqctrl, SYS_FREQCTRL0); 182 break; 183 } 184 185 /* 186 * Route 48MHz FREQ2 into USB Host and/or Device 187 */ 188#ifdef CONFIG_USB_OHCI 189 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); 190#endif 191#ifdef CONFIG_AU1X00_USB_DEVICE 192 sys_clksrc |= ((4<<7) | (0<<6) | (0<<5)); 193#endif 194 au_writel(sys_clksrc, SYS_CLKSRC); 195 196#ifdef CONFIG_USB_OHCI 197 // enable host controller and wait for reset done 198 au_writel(0x08, USB_HOST_CONFIG); 199 udelay(1000); 200 au_writel(0x0E, USB_HOST_CONFIG); 201 udelay(1000); 202 au_readl(USB_HOST_CONFIG); // throw away first read 203 while (!(au_readl(USB_HOST_CONFIG) & 0x10)) 204 au_readl(USB_HOST_CONFIG); 205#endif 206 207 // configure pins GPIO[14:9] as GPIO 208 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080); 209 210#ifndef CONFIG_AU1X00_USB_DEVICE 211 // 2nd USB port is USB host 212 pin_func |= 0x8000; 213#endif 214 au_writel(pin_func, SYS_PINFUNC); 215 au_writel(0x2800, SYS_TRIOUTCLR); 216 au_writel(0x0030, SYS_OUTPUTCLR); 217#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) 218 219 // make gpio 15 an input (for interrupt line) 220 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100); 221 // we don't need I2S, so make it available for GPIO[31:29] 222 pin_func |= (1<<5); 223 au_writel(pin_func, SYS_PINFUNC); 224 225 au_writel(0x8000, SYS_TRIOUTCLR); 226 227#ifdef CONFIG_FB 228 conswitchp = &dummy_con; 229#endif 230 231 static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00); 232 au_writel(static_cfg0, MEM_STCFG0); 233 234 // configure RCE2* for LCD 235 au_writel(0x00000004, MEM_STCFG2); 236 237 // MEM_STTIME2 238 au_writel(0x09000000, MEM_STTIME2); 239 240 // Set 32-bit base address decoding for RCE2* 241 au_writel(0x10003ff0, MEM_STADDR2); 242 243 // PCI CPLD setup 244 // expand CE0 to cover PCI 245 au_writel(0x11803e40, MEM_STADDR1); 246 247 // burst visibility on 248 au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0); 249 250 au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing 251 au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA 252 253 /* setup the static bus controller */ 254 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ 255 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ 256 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ 257 258#ifdef CONFIG_FB_E1356 259 if ((argptr = strstr(argptr, "video=")) == NULL) { 260 argptr = prom_getcmdline(); 261 strcat(argptr, " video=e1356fb:system:pb1000,mmunalign:1"); 262 } 263#endif // CONFIG_FB_E1356 264 265 266#ifdef CONFIG_PCI 267 au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0 268 au_writel(0, SDRAM_MBAR); // set mbar to 0 269 au_writel(0x2, SDRAM_CMD); // enable memory accesses 270 au_sync_delay(1); 271#endif 272 273#ifndef CONFIG_SERIAL_NONSTANDARD 274 /* don't touch the default serial console */ 275 au_writel(0, UART0_ADDR + UART_CLK); 276#endif 277 au_writel(0, UART1_ADDR + UART_CLK); 278 au_writel(0, UART2_ADDR + UART_CLK); 279 au_writel(0, UART3_ADDR + UART_CLK); 280 281#ifdef CONFIG_BLK_DEV_IDE 282 ide_ops = &std_ide_ops; 283#endif 284 285 // setup irda clocks 286 // aux clock, divide by 2, clock from 2/4 divider 287 au_writel(au_readl(SYS_CLKSRC) | 0x7, SYS_CLKSRC); 288 pin_func = au_readl(SYS_PINFUNC) & (u32)(~(1<<2)); // clear IRTXD 289 au_writel(pin_func, SYS_PINFUNC); 290 291 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); 292 au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); 293 au_sync(); 294 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); 295 au_writel(0, SYS_TOYTRIM); 296 297 /* Enable Au1000 BCLK switching - note: sed1356 must not use 298 * its BCLK (Au1000 LCLK) for any timings */ 299 switch (prid & 0x000000FF) 300 { 301 case 0x00: /* DA */ 302 case 0x01: /* HA */ 303 case 0x02: /* HB */ 304 break; 305 default: /* HC and newer */ 306 au_writel(0x00000060, 0xb190003c); 307 break; 308 } 309} 310