Searched refs:NCR5380_write (Results 1 - 21 of 21) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/scsi/
H A DNCR5380.c186 * NCR5380_write(register, value) - write to the specific register
621 NCR5380_write(TARGET_COMMAND_REG, 0);
622 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
623 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);
624 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_SEL);
629 NCR5380_write(SELECT_ENABLE_REG, 0);
630 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
920 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
921 NCR5380_write(MODE_REG, MR_BASE);
922 NCR5380_write(TARGET_COMMAND_RE
[all...]
H A Dmac_NCR5380.c133 * NCR5380_write(register, value) - write to the specific register
802 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
803 NCR5380_write(MODE_REG, MR_BASE);
804 NCR5380_write(TARGET_COMMAND_REG, 0);
805 NCR5380_write(SELECT_ENABLE_REG, 0);
1127 NCR5380_write(MODE_REG, MR_BASE);
1128 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1327 NCR5380_write(TARGET_COMMAND_REG, 0);
1334 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);
1335 NCR5380_write(MODE_RE
[all...]
H A Dsun3_NCR5380.c117 * NCR5380_write(register, value) - write to the specific register
784 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
785 NCR5380_write(MODE_REG, MR_BASE);
786 NCR5380_write(TARGET_COMMAND_REG, 0);
787 NCR5380_write(SELECT_ENABLE_REG, 0);
1127 NCR5380_write(MODE_REG, MR_BASE);
1128 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1313 NCR5380_write(TARGET_COMMAND_REG, 0);
1320 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);
1321 NCR5380_write(MODE_RE
[all...]
H A Datari_NCR5380.c115 * NCR5380_write(register, value) - write to the specific register
789 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
790 NCR5380_write(MODE_REG, MR_BASE);
791 NCR5380_write(TARGET_COMMAND_REG, 0);
792 NCR5380_write(SELECT_ENABLE_REG, 0);
1136 NCR5380_write(MODE_REG, MR_BASE);
1137 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1336 NCR5380_write(TARGET_COMMAND_REG, 0);
1343 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);
1344 NCR5380_write(MODE_RE
[all...]
H A Ddtc.c251 NCR5380_write(DTC_CONTROL_REG, CSR_5380_INTR); /* Enable int's */
334 NCR5380_write(MODE_REG, MR_ENABLE_EOP_INTR | MR_DMA_MODE);
336 NCR5380_write(DTC_CONTROL_REG, CSR_DIR_READ);
338 NCR5380_write(DTC_CONTROL_REG, CSR_DIR_READ | CSR_INT_BASE);
339 NCR5380_write(DTC_BLK_CNT, len >> 7); /* Block count */
356 NCR5380_write(MODE_REG, 0); /* Clear the operating mode */
381 NCR5380_write(MODE_REG, MR_ENABLE_EOP_INTR | MR_DMA_MODE);
384 NCR5380_write(DTC_CONTROL_REG, 0);
386 NCR5380_write(DTC_CONTROL_REG, CSR_5380_INTR);
387 NCR5380_write(DTC_BLK_CN
[all...]
H A Ddtc.h95 #define NCR5380_write(reg, value) (isa_writeb(value, DTC_address(reg))) macro
102 #define NCR5380_write(reg, value) do { \ macro
H A Dt128.h160 #define NCR5380_write(reg, value) isa_writeb((value),(T128_address(reg))) macro
166 #define NCR5380_write(reg, value) { \ macro
H A Dg_NCR5380.h114 #define NCR5380_write(reg, value) (outb((value), (NCR5380_map_name + (reg)))) macro
130 #define NCR5380_write(reg, value) isa_writeb(NCR5380_map_name + NCR53C400_mem_base + (reg), value) macro
H A Dpas16.h171 #define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) ) macro
177 #define NCR5380_write(reg, value) \ macro
H A Ddmx3191d.h52 #define NCR5380_write(reg, value) outb(value, port + reg) macro
H A Dmac_scsi.h108 #define NCR5380_write(reg, value) macscsi_write(_instance, reg, value) macro
H A Dg_NCR5380.c543 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE | CSR_TRANS_DIR);
544 NCR5380_write(C400_BLOCK_COUNTER_REG, blocks);
595 NCR5380_write(MODE_REG, MR_BASE);
601 * NCR5380_write - pseudo DMA write
620 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE);
621 NCR5380_write(C400_BLOCK_COUNTER_REG, blocks);
636 NCR5380_write(C400_HOST_BUFFER, src[start + i]);
652 NCR5380_write(C400_HOST_BUFFER, src[start + i]);
H A Dsun3_scsi.c365 NCR5380_write( TARGET_COMMAND_REG,
369 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );
375 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
H A Dpas16.c296 NCR5380_write(MODE_REG, 0x20); /* Is it really SCSI? */
299 NCR5380_write(MODE_REG, 0x00); /* it back. */
H A Dmac_scsi.c337 NCR5380_write( TARGET_COMMAND_REG,
341 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );
345 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
H A Datari_scsi.c833 NCR5380_write( TARGET_COMMAND_REG,
837 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );
841 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
1070 * NCR5380_write call these functions via function pointers.
H A Datari_scsi.h71 #define NCR5380_write(reg, value) atari_scsi_reg_write( reg, value ) macro
H A Dsun3_scsi.h120 #define NCR5380_write(reg, value) sun3scsi_write(reg, value) macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/acorn/scsi/
H A Decoscsi.c201 #define NCR5380_write(reg, value) ecoscsi_write(_instance, reg, value) macro
H A Doak.c85 #define NCR5380_write(reg, value) oakscsi_write(_instance, reg, value) macro
H A Dcumana_1.c103 #define NCR5380_write(reg, value) cumanascsi_write(_instance, reg, value) macro

Completed in 102 milliseconds