1/* 2 * Trantor T128/T128F/T228 defines 3 * Note : architecturally, the T100 and T128 are different and won't work 4 * 5 * Copyright 1993, Drew Eckhardt 6 * Visionary Computing 7 * (Unix and Linux consulting and custom programming) 8 * drew@colorado.edu 9 * +1 (303) 440-4894 10 * 11 * DISTRIBUTION RELEASE 3. 12 * 13 * For more information, please consult 14 * 15 * Trantor Systems, Ltd. 16 * T128/T128F/T228 SCSI Host Adapter 17 * Hardware Specifications 18 * 19 * Trantor Systems, Ltd. 20 * 5415 Randall Place 21 * Fremont, CA 94538 22 * 1+ (415) 770-1400, FAX 1+ (415) 770-9910 23 * 24 * and 25 * 26 * NCR 5380 Family 27 * SCSI Protocol Controller 28 * Databook 29 * 30 * NCR Microelectronics 31 * 1635 Aeroplaza Drive 32 * Colorado Springs, CO 80916 33 * 1+ (719) 578-3400 34 * 1+ (800) 334-5454 35 */ 36 37/* 38 * $Log: t128.h,v $ 39 * Revision 1.1.1.1 2008/10/15 03:26:55 james26_jang 40 * Initial. 41 * 42 * Revision 1.1.1.1 2008/07/21 09:15:24 james26_jang 43 * New UI, New QoS, New wireless driver(4.151.10.29), ipmonitor. 44 * 45 * Revision 1.1.1.1 2008/07/02 14:39:42 james26_jang 46 * 4.100.10.29, New QoS and New UI. 47 * 48 * Revision 1.1.1.1 2003/02/03 22:37:54 mhuang 49 * LINUX_2_4 branch snapshot from linux-mips.org CVS 50 * 51 */ 52 53#ifndef T128_H 54#define T128_H 55 56#define T128_PUBLIC_RELEASE 3 57 58#define TDEBUG_INIT 0x1 59#define TDEBUG_TRANSFER 0x2 60 61/* 62 * The trantor boards are memory mapped. They use an NCR5380 or 63 * equivalent (my sample board had part second sourced from ZILOG). 64 * NCR's recommended "Pseudo-DMA" architecture is used, where 65 * a PAL drives the DMA signals on the 5380 allowing fast, blind 66 * transfers with proper handshaking. 67 */ 68 69/* 70 * Note : a boot switch is provided for the purpose of informing the 71 * firmware to boot or not boot from attached SCSI devices. So, I imagine 72 * there are fewer people who've yanked the ROM like they do on the Seagate 73 * to make bootup faster, and I'll probably use this for autodetection. 74 */ 75#define T_ROM_OFFSET 0 76 77/* 78 * Note : my sample board *WAS NOT* populated with the SRAM, so this 79 * can't be used for autodetection without a ROM present. 80 */ 81#define T_RAM_OFFSET 0x1800 82 83/* 84 * All of the registers are allocated 32 bytes of address space, except 85 * for the data register (read/write to/from the 5380 in pseudo-DMA mode) 86 */ 87#define T_CONTROL_REG_OFFSET 0x1c00 /* rw */ 88#define T_CR_INT 0x10 /* Enable interrupts */ 89#define T_CR_CT 0x02 /* Reset watchdog timer */ 90 91#define T_STATUS_REG_OFFSET 0x1c20 /* ro */ 92#define T_ST_BOOT 0x80 /* Boot switch */ 93#define T_ST_S3 0x40 /* User settable switches, */ 94#define T_ST_S2 0x20 /* read 0 when switch is on, 1 off */ 95#define T_ST_S1 0x10 96#define T_ST_PS2 0x08 /* Set for Microchannel 228 */ 97#define T_ST_RDY 0x04 /* 5380 DRQ */ 98#define T_ST_TIM 0x02 /* indicates 40us watchdog timer fired */ 99#define T_ST_ZERO 0x01 /* Always zero */ 100 101#define T_5380_OFFSET 0x1d00 /* 8 registers here, see NCR5380.h */ 102 103#define T_DATA_REG_OFFSET 0x1e00 /* rw 512 bytes long */ 104 105#ifndef ASM 106int t128_abort(Scsi_Cmnd *); 107int t128_biosparam(Disk *, kdev_t, int*); 108int t128_detect(Scsi_Host_Template *); 109int t128_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *)); 110int t128_reset(Scsi_Cmnd *, unsigned int reset_flags); 111int t128_proc_info (char *buffer, char **start, off_t offset, 112 int length, int hostno, int inout); 113 114#ifndef NULL 115#define NULL 0 116#endif 117 118#ifndef CMD_PER_LUN 119#define CMD_PER_LUN 2 120#endif 121 122#ifndef CAN_QUEUE 123#define CAN_QUEUE 32 124#endif 125 126/* 127 * I hadn't thought of this with the earlier drivers - but to prevent 128 * macro definition conflicts, we shouldn't define all of the internal 129 * macros when this is being used solely for the host stub. 130 */ 131 132#define TRANTOR_T128 { \ 133 name: "Trantor T128/T128F/T228", \ 134 detect: t128_detect, \ 135 queuecommand: t128_queue_command, \ 136 abort: t128_abort, \ 137 reset: t128_reset, \ 138 bios_param: t128_biosparam, \ 139 can_queue: CAN_QUEUE, \ 140 this_id: 7, \ 141 sg_tablesize: SG_ALL, \ 142 cmd_per_lun: CMD_PER_LUN, \ 143 use_clustering: DISABLE_CLUSTERING} 144 145#ifndef HOSTS_C 146 147#define NCR5380_implementation_fields \ 148 unsigned long base 149 150#define NCR5380_local_declare() \ 151 unsigned long base 152 153#define NCR5380_setup(instance) \ 154 base = (instance)->base 155 156#define T128_address(reg) (base + T_5380_OFFSET + ((reg) * 0x20)) 157 158#if !(TDEBUG & TDEBUG_TRANSFER) 159#define NCR5380_read(reg) isa_readb(T128_address(reg)) 160#define NCR5380_write(reg, value) isa_writeb((value),(T128_address(reg))) 161#else 162#define NCR5380_read(reg) \ 163 (((unsigned char) printk("scsi%d : read register %d at address %08x\n"\ 164 , instance->hostno, (reg), T128_address(reg))), isa_readb(T128_address(reg))) 165 166#define NCR5380_write(reg, value) { \ 167 printk("scsi%d : write %02x to register %d at address %08x\n", \ 168 instance->hostno, (value), (reg), T128_address(reg)); \ 169 isa_writeb((value), (T128_address(reg))); \ 170} 171#endif 172 173#define NCR5380_intr t128_intr 174#define do_NCR5380_intr do_t128_intr 175#define NCR5380_queue_command t128_queue_command 176#define NCR5380_abort t128_abort 177#define NCR5380_reset t128_reset 178#define NCR5380_proc_info t128_proc_info 179 180/* 15 14 12 10 7 5 3 181 1101 0100 1010 1000 */ 182 183#define T128_IRQS 0xc4a8 184 185#endif /* else def HOSTS_C */ 186#endif /* ndef ASM */ 187#endif /* T128_H */ 188