Searched refs:NCR5380_read (Results 1 - 21 of 21) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/scsi/
H A DNCR5380.c184 * NCR5380_read(register) - read from the specified register
323 data = NCR5380_read(CURRENT_SCSI_DATA_REG);
324 status = NCR5380_read(STATUS_REG);
325 mr = NCR5380_read(MODE_REG);
326 icr = NCR5380_read(INITIATOR_COMMAND_REG);
327 basr = NCR5380_read(BUS_AND_STATUS_REG);
377 status = NCR5380_read(STATUS_REG);
943 for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) {
950 while (time_before(jiffies, timeout) && (NCR5380_read(STATUS_REG) & SR_BSY));
1219 basr = NCR5380_read(BUS_AND_STATUS_RE
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H A Dmac_NCR5380.c131 * NCR5380_read(register) - read from the specified register
483 data = NCR5380_read(CURRENT_SCSI_DATA_REG);
484 status = NCR5380_read(STATUS_REG);
485 mr = NCR5380_read(MODE_REG);
486 icr = NCR5380_read(INITIATOR_COMMAND_REG);
487 basr = NCR5380_read(BUS_AND_STATUS_REG);
529 status = NCR5380_read(STATUS_REG);
1112 if ((((NCR5380_read(BUS_AND_STATUS_REG)) &
1115 saved_data = NCR5380_read(INPUT_DATA_REG);
1123 HOSTNO, NCR5380_read(BUS_AND_STATUS_RE
[all...]
H A Ddtc.c333 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
343 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY)
354 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS))
358 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
380 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
391 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY)
399 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS))
403 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT))
H A Dsun3_NCR5380.c115 * NCR5380_read(register) - read from the specified register
468 data = NCR5380_read(CURRENT_SCSI_DATA_REG);
469 status = NCR5380_read(STATUS_REG);
470 mr = NCR5380_read(MODE_REG);
471 icr = NCR5380_read(INITIATOR_COMMAND_REG);
472 basr = NCR5380_read(BUS_AND_STATUS_REG);
514 status = NCR5380_read(STATUS_REG);
1101 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG),
1102 NCR5380_read(STATUS_REG));
1112 if((NCR5380_read(BUS_AND_STATUS_RE
[all...]
H A Datari_NCR5380.c113 * NCR5380_read(register) - read from the specified register
466 data = NCR5380_read(CURRENT_SCSI_DATA_REG);
467 status = NCR5380_read(STATUS_REG);
468 mr = NCR5380_read(MODE_REG);
469 icr = NCR5380_read(INITIATOR_COMMAND_REG);
470 basr = NCR5380_read(BUS_AND_STATUS_REG);
512 status = NCR5380_read(STATUS_REG);
1121 if ((((NCR5380_read(BUS_AND_STATUS_REG)) &
1124 saved_data = NCR5380_read(INPUT_DATA_REG);
1132 HOSTNO, NCR5380_read(BUS_AND_STATUS_RE
[all...]
H A Dg_NCR5380.c546 if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) {
549 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) {
553 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY);
559 dst[start + i] = NCR5380_read(C400_HOST_BUFFER);
570 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY)
579 dst[start + i] = NCR5380_read(C400_HOST_BUFFER);
589 if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ))
592 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER))
596 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
623 if (NCR5380_read(C400_CONTROL_STATUS_RE
[all...]
H A Ddtc.h94 #define NCR5380_read(reg) (isa_readb(DTC_address(reg))) macro
97 #define NCR5380_read(reg) (isa_readb(DTC_address(reg))) macro
H A Dt128.h159 #define NCR5380_read(reg) isa_readb(T128_address(reg)) macro
162 #define NCR5380_read(reg) \ macro
H A Dg_NCR5380.h113 #define NCR5380_read(reg) (inb(NCR5380_map_name + (reg))) macro
129 #define NCR5380_read(reg) isa_readb(NCR5380_map_name + NCR53C400_mem_base + (reg)) macro
H A Dpas16.h170 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) ) macro
173 #define NCR5380_read(reg) \ macro
H A Ddmx3191d.h51 #define NCR5380_read(reg) inb(port + reg) macro
H A Dmac_scsi.h107 #define NCR5380_read(reg) macscsi_read(_instance, reg) macro
H A Dsun3_scsi.c366 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
376 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
565 if(count && (NCR5380_read(BUS_AND_STATUS_REG) &
568 printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG));
H A Dpas16.c227 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
297 if (NCR5380_read(MODE_REG) != 0x20) /* Write to a reg. */
300 if (NCR5380_read(MODE_REG) != 0x00)
H A Dmac_scsi.c338 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
346 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
615 if(NCR5380_read(BUS_AND_STATUS_REG)&BASR_IRQ)
H A Datari_scsi.h70 #define NCR5380_read(reg) atari_scsi_reg_read( reg ) macro
H A Dsun3_scsi.h119 #define NCR5380_read(reg) sun3scsi_read(reg) macro
H A Datari_scsi.c834 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
842 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
1069 * methods are quite different. The calling macros NCR5380_read and
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/acorn/scsi/
H A Decoscsi.c200 #define NCR5380_read(reg) ecoscsi_read(_instance, reg) macro
H A Doak.c84 #define NCR5380_read(reg) oakscsi_read(_instance, reg) macro
H A Dcumana_1.c102 #define NCR5380_read(reg) cumanascsi_read(_instance, reg) macro

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