Searched refs:MII_BMCR (Results 1 - 25 of 28) sorted by relevance

12

/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/net/
H A Dmii.c66 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
141 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
143 mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr);
150 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
160 mii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp);
182 bmcr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMCR);
186 mii->mdio_write(mii->dev, mii->phy_id, MII_BMCR, bmcr);
302 case MII_BMCR: {
H A Dsungem.c1071 ctl = phy_read(gp, MII_BMCR);
1080 phy_write(gp, MII_BMCR, ctl);
1144 val = phy_read(gp, MII_BMCR);
1249 phy_write(gp, MII_BMCR, gp->link_fcntl);
1253 val = phy_read(gp, MII_BMCR);
1262 phy_write(gp, MII_BMCR, val);
1270 val = phy_read(gp, MII_BMCR);
1273 phy_write(gp, MII_BMCR, val);
1336 u16 cntl = phy_read(gp, MII_BMCR);
1354 gp->link_fcntl = phy_read(gp, MII_BMCR);
[all...]
H A Dioc3-eth.c720 ip->sw_bmcr = mii_read(ip, MII_BMCR);
725 mii_write(ip, MII_BMCR, ip->sw_bmcr);
733 mii_write(ip, MII_BMCR, ip->sw_bmcr);
769 ip->sw_bmcr = mii_read(ip, MII_BMCR);
807 ip->sw_bmcr = mii_read(ip, MII_BMCR);
858 ip->sw_bmcr = mii_read(ip, MII_BMCR);
862 mii_write(ip, MII_BMCR, ip->sw_bmcr);
1021 ip->sw_bmcr = mii_read(ip, MII_BMCR);
1063 mii_write(ip, MII_BMCR, ip->sw_bmcr);
1067 mii_write(ip, MII_BMCR, i
[all...]
H A Ddl2k.c1370 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1428 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1433 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1443 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1445 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1449 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1474 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1562 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1567 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1574 mii_write (dev, phy_addr, MII_BMCR, bmc
[all...]
H A Dsunhme.c561 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
568 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
575 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
613 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
645 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
718 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
722 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1012 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1014 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1028 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
[all...]
H A Dstarfire.c769 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
773 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
1021 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1023 while (mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET);
1025 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1040 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1527 mdio_read(dev, np->phys[0], MII_BMCR);
1530 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1793 tmp = mdio_read(dev, np->phys[0], MII_BMCR);
1796 mdio_write(dev, np->phys[0], MII_BMCR, tm
[all...]
H A Deepro100.c787 mdio_write(dev, eeprom[6] & 0x1f, MII_BMCR,
1012 mdio_write(dev, phy_addr, MII_BMCR, mii_ctrl[dev->default_port & 7]);
1014 mdio_write(dev, phy_addr, MII_BMCR, 0x3300);
1056 mdio_read(dev, sp->phy[0] & 0x1f, MII_BMCR);
1340 int mii_bmcr = mdio_read(dev, phy_addr, MII_BMCR);
1341 mdio_write(dev, phy_addr, MII_BMCR, 0x0400);
1344 mdio_write(dev, phy_addr, MII_BMCR, 0x8000);
1346 mdio_write(dev, phy_addr, MII_BMCR, mii_ctrl[dev->default_port & 7]);
1348 mdio_read(dev, phy_addr, MII_BMCR);
1349 mdio_write(dev, phy_addr, MII_BMCR, mii_bmc
[all...]
H A Dnatsemi.c1693 if (mdio_read(dev, 1, MII_BMCR) & BMCR_ANENABLE
1965 tmp = mdio_read(dev, 1, MII_BMCR);
1968 mdio_write(dev, 1, MII_BMCR, tmp);
2176 tmp = mdio_read(dev, 1, MII_BMCR);
2221 tmp = mdio_read(dev, 1, MII_BMCR);
2236 mdio_write(dev, 1, MII_BMCR, tmp);
H A Dsundance.c679 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET);
681 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
687 mdio_write (dev, np->phys[0], MII_BMCR, mii_ctl);
1441 mii_ctl = mdio_read (dev, np->phys[0], MII_BMCR);
H A Dtg3.c393 err = tg3_writephy(tp, MII_BMCR, phy_control);
399 err = tg3_readphy(tp, MII_BMCR, &phy_control);
824 tg3_readphy(tp, MII_BMCR, &orig_bmcr);
826 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
838 tg3_writephy(tp, MII_BMCR, bmcr);
842 tg3_writephy(tp, MII_BMCR,
994 tg3_readphy(tp, MII_BMCR, &bmcr);
995 tg3_readphy(tp, MII_BMCR, &bmcr);
1480 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5091 tg3_readphy(tp, MII_BMCR,
[all...]
H A Dvia-rhine.c818 mdio_write(dev, np->phys[0], MII_BMCR,
1064 case MII_BMCR: /* Is user forcing speed/duplex? */
1536 mdio_write(dev, np->phys[0], MII_BMCR, 0x3300);
H A Ddl2k.h273 MII_BMCR = 0, enumerator in enum:_mii_reg
H A Dsb1250-mac.c439 #define MII_BMCR 0x00 /* Basic mode control register (rw) */ macro
2488 bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
H A Depic100.c719 mdio_write(dev, ep->phys[0], MII_BMCR, media2miictl[dev->if_port&15]);
732 mdio_write(dev, ep->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/net/e100/
H A De100_phy.c141 e100_mdi_read(bdp, MII_BMCR, phy_address, &ctrl_reg);
217 e100_mdi_write(bdp, MII_BMCR, phy_address,
221 e100_mdi_read(bdp, MII_BMCR, bdp->phy_addr, &ctrl_reg);
223 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg);
360 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr,
631 e100_mdi_read(bdp, MII_BMCR, bdp->phy_addr, &control);
666 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, control);
806 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr,
857 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg);
867 e100_mdi_write(bdp, MII_BMCR, bd
[all...]
/asus-wl-520gu-7.0.1.45/src/cfe/cfe/net/
H A Dmii.h61 #define MII_BMCR 0x00 /* Basic Mode Control (rw) */ macro
/asus-wl-520gu-7.0.1.45/src/cfe/cfe/arch/mips/cpu/sb1250/src/
H A Ddev_sb1250_ethernet.c1760 bmcr = sbeth_mii_read(s,s->sbe_phyaddr,MII_BMCR);
1889 sbeth_mii_write(s,1,MII_BMCR,0x1340);
2232 miireg = sbeth_mii_read(s,s->sbe_phyaddr,MII_BMCR);
2236 sbeth_mii_write(s,s->sbe_phyaddr,MII_BMCR,miireg);
2257 miireg = sbeth_mii_read(s,s->sbe_phyaddr,MII_BMCR);
2259 sbeth_mii_write(s,s->sbe_phyaddr,MII_BMCR,miireg);
2287 sbeth_mii_write(s,s->sbe_phyaddr,MII_BMCR,
2297 sbeth_mii_write(s,s->sbe_phyaddr,MII_BMCR,
2306 sbeth_mii_write(s,s->sbe_phyaddr,MII_BMCR,
2315 sbeth_mii_write(s,s->sbe_phyaddr,MII_BMCR,
[all...]
/asus-wl-520gu-7.0.1.45/src/cfe/cfe/dev/
H A Ddev_dp83815.c1157 control = mii_read_register(sc, MII_BMCR);
1160 mii_write_register(sc, MII_BMCR, control);
1178 mii_write_register(sc, MII_BMCR, control);
1197 control = mii_read_register(sc, MII_BMCR);
1200 mii_write_register(sc, MII_BMCR, BMCR_RESET);
1203 control = mii_read_register(sc, MII_BMCR);
1219 mii_write_register(sc, MII_BMCR, control);
1258 mii_write_register(sc, MII_BMCR, control);
1262 mii_write_register(sc, MII_BMCR, control);
H A Ddev_tulip.c1242 control = mii_read_register(sc, MII_BMCR);
1246 mii_write_register(sc, MII_BMCR, control);
1270 mii_write_register(sc, MII_BMCR, control);
1295 control = mii_read_register(sc, MII_BMCR);
1298 mii_write_register(sc, MII_BMCR, BMCR_RESET);
1301 control = mii_read_register(sc, MII_BMCR);
1317 mii_write_register(sc, MII_BMCR, control);
1361 mii_write_register(sc, MII_BMCR, control);
1366 mii_write_register(sc, MII_BMCR, control);
H A Ddev_bcm5700.c1238 control = mii_read_register(sc, sc->phy_addr, MII_BMCR);
1241 mii_write_register(sc, sc->phy_addr, MII_BMCR, control);
1259 mii_write_register(sc, sc->phy_addr, MII_BMCR, control);
1279 control = mii_read_register(sc, sc->phy_addr, MII_BMCR);
2270 mii_write_register(sc, sc->phy_addr, MII_BMCR, BMCR_RESET);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/linux/
H A Dmii.h15 #define MII_BMCR 0x00 /* Basic mode control register */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/linux/
H A Dmii.h15 #define MII_BMCR 0x00 /* Basic mode control register */ macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/net/tulip/
H A Dmedia.c480 mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR);
551 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
554 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/net/pcmcia/
H A Dxircom_tulip_cb.c468 int mii_reg0 = mdio_read(dev, phy, MII_BMCR);
973 mdio_read(dev, tp->phys[0], MII_BMCR);
976 reg0 = mdio_read(dev, tp->phys[0], MII_BMCR);
1029 mdio_write(dev, tp->phys[0], MII_BMCR, BMCR_RESET);
1031 while (mdio_read(dev, tp->phys[0], MII_BMCR) & BMCR_RESET);
1033 reg0 = mdio_read(dev, tp->phys[0], MII_BMCR);
1050 mdio_write(dev, tp->phys[0], MII_BMCR, reg0);
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/usb/
H A Dusbnet.c661 dev->mii.phy_id, MII_BMCR, 2, buf16)) < 0) {
662 dbg("Failed to write MII reg - MII_BMCR: %02x", ret);
677 dev->mii.phy_id, MII_BMCR,

Completed in 463 milliseconds

12