1/* 2 * Copyright (C) 2001 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19/* 20 This driver is designed for the Broadcom BCM12500 SOC chip's built-in 21 Ethernet controllers. 22 23 The author may be reached as mpl@broadcom.com 24*/ 25 26 27 28#define CONFIG_SBMAC_COALESCE 29 30/* A few user-configurable values. 31 These may be modified when a driver module is loaded. */ 32 33static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ 34 35/* Used to pass the media type, etc. 36 Both 'options[]' and 'full_duplex[]' should exist for driver 37 interoperability. 38 The media type is usually passed in 'options[]'. 39*/ 40 41#define MAX_UNITS 3 /* More are supported, limit only on options */ 42#ifdef MODULE 43static int options[MAX_UNITS] = {-1, -1, -1}; 44static int full_duplex[MAX_UNITS] = {-1, -1, -1}; 45#endif 46 47#ifdef CONFIG_SBMAC_COALESCE 48static int int_pktcnt = 0; 49static int int_timeout = 0; 50#endif 51 52/* Operational parameters that usually are not changed. */ 53 54/* Time in jiffies before concluding the transmitter is hung. */ 55#define TX_TIMEOUT (2*HZ) 56 57#if !defined(__OPTIMIZE__) || !defined(__KERNEL__) 58#warning You must compile this file with the correct options! 59#warning See the last lines of the source file. 60#error You must compile this driver with "-O". 61#endif 62 63#include <linux/module.h> 64#include <linux/kernel.h> 65#include <linux/string.h> 66#include <linux/timer.h> 67#include <linux/errno.h> 68#include <linux/ioport.h> 69#include <linux/slab.h> 70#include <linux/interrupt.h> 71#include <linux/netdevice.h> 72#include <linux/etherdevice.h> 73#include <linux/skbuff.h> 74#include <linux/init.h> 75#include <linux/config.h> 76#include <asm/processor.h> /* Processor type for cache alignment. */ 77#include <asm/bitops.h> 78#include <asm/io.h> 79#include <asm/sibyte/sb1250.h> 80#include <asm/sibyte/64bit.h> 81#include <asm/cache.h> 82 83/* This is only here until the firmware is ready. In that case, 84 the firmware leaves the ethernet address in the register for us. */ 85#ifdef CONFIG_SIBYTE_STANDALONE 86#define SBMAC_ETH0_HWADDR "40:00:00:00:01:00" 87#define SBMAC_ETH1_HWADDR "40:00:00:00:01:01" 88#define SBMAC_ETH2_HWADDR "40:00:00:00:01:02" 89#endif 90 91 92/* These identify the driver base version and may not be removed. */ 93 94 95 96MODULE_AUTHOR("Mitch Lichtenberg (mpl@broadcom.com)"); 97MODULE_DESCRIPTION("Broadcom BCM12500 SOC GB Ethernet driver"); 98MODULE_PARM(debug, "i"); 99MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i"); 100MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i"); 101 102MODULE_PARM(int_pktcnt, "i"); 103MODULE_PARM(int_timeout, "i"); 104 105#include <asm/sibyte/sb1250_defs.h> 106#include <asm/sibyte/sb1250_regs.h> 107#include <asm/sibyte/sb1250_mac.h> 108#include <asm/sibyte/sb1250_dma.h> 109#include <asm/sibyte/sb1250_int.h> 110#include <asm/sibyte/sb1250_scd.h> /* Only to check SOC part number. */ 111 112 113/********************************************************************** 114 * Simple types 115 ********************************************************************* */ 116 117 118typedef unsigned long sbmac_port_t; 119 120typedef enum { sbmac_speed_auto, sbmac_speed_10, 121 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; 122 123typedef enum { sbmac_duplex_auto, sbmac_duplex_half, 124 sbmac_duplex_full } sbmac_duplex_t; 125 126typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, 127 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; 128 129typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, 130 sbmac_state_broken } sbmac_state_t; 131 132 133/********************************************************************** 134 * Macros 135 ********************************************************************* */ 136 137 138#define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ 139 (d)->sbdma_dscrtable : (d)->f+1) 140 141 142#define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES) 143 144#define SBMAC_READCSR(t) in64((unsigned long)t) 145#define SBMAC_WRITECSR(t,v) out64(v, (unsigned long)t) 146 147 148#define SBMAC_MAX_TXDESCR 32 149#define SBMAC_MAX_RXDESCR 32 150 151#define ETHER_ALIGN 2 152#define ETHER_ADDR_LEN 6 153#define ENET_PACKET_SIZE 1518 154/*#define ENET_PACKET_SIZE 9216 */ 155 156/********************************************************************** 157 * DMA Descriptor structure 158 ********************************************************************* */ 159 160typedef struct sbdmadscr_s { 161 uint64_t dscr_a; 162 uint64_t dscr_b; 163} sbdmadscr_t; 164 165typedef unsigned long paddr_t; 166 167/********************************************************************** 168 * DMA Controller structure 169 ********************************************************************* */ 170 171typedef struct sbmacdma_s { 172 173 /* 174 * This stuff is used to identify the channel and the registers 175 * associated with it. 176 */ 177 178 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */ 179 int sbdma_channel; /* channel number */ 180 int sbdma_txdir; /* direction (1=transmit) */ 181 int sbdma_maxdescr; /* total # of descriptors in ring */ 182#ifdef CONFIG_SBMAC_COALESCE 183 int sbdma_int_pktcnt; /* # descriptors rx before interrupt*/ 184 int sbdma_int_timeout; /* # usec rx interrupt */ 185#endif 186 187 sbmac_port_t sbdma_config0; /* DMA config register 0 */ 188 sbmac_port_t sbdma_config1; /* DMA config register 1 */ 189 sbmac_port_t sbdma_dscrbase; /* Descriptor base address */ 190 sbmac_port_t sbdma_dscrcnt; /* Descriptor count register */ 191 sbmac_port_t sbdma_curdscr; /* current descriptor address */ 192 193 /* 194 * This stuff is for maintenance of the ring 195 */ 196 197 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */ 198 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */ 199 200 struct sk_buff **sbdma_ctxtable; /* context table, one per descr */ 201 202 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */ 203 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */ 204 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */ 205} sbmacdma_t; 206 207 208/********************************************************************** 209 * Ethernet softc structure 210 ********************************************************************* */ 211 212struct sbmac_softc { 213 214 /* 215 * Linux-specific things 216 */ 217 218 struct net_device *sbm_dev; /* pointer to linux device */ 219 spinlock_t sbm_lock; /* spin lock */ 220 struct timer_list sbm_timer; /* for monitoring MII */ 221 struct net_device_stats sbm_stats; 222 int sbm_devflags; /* current device flags */ 223 224 int sbm_phy_oldbmsr; 225 int sbm_phy_oldanlpar; 226 int sbm_phy_oldk1stsr; 227 int sbm_phy_oldlinkstat; 228 int sbm_buffersize; 229 230 unsigned char sbm_phys[2]; 231 232 /* 233 * Controller-specific things 234 */ 235 236 unsigned long sbm_base; /* MAC's base address */ 237 sbmac_state_t sbm_state; /* current state */ 238 239 sbmac_port_t sbm_macenable; /* MAC Enable Register */ 240 sbmac_port_t sbm_maccfg; /* MAC Configuration Register */ 241 sbmac_port_t sbm_fifocfg; /* FIFO configuration register */ 242 sbmac_port_t sbm_framecfg; /* Frame configuration register */ 243 sbmac_port_t sbm_rxfilter; /* receive filter register */ 244 sbmac_port_t sbm_isr; /* Interrupt status register */ 245 sbmac_port_t sbm_imr; /* Interrupt mask register */ 246 sbmac_port_t sbm_mdio; /* MDIO register */ 247 248 sbmac_speed_t sbm_speed; /* current speed */ 249 sbmac_duplex_t sbm_duplex; /* current duplex */ 250 sbmac_fc_t sbm_fc; /* current flow control setting */ 251 252 unsigned char sbm_hwaddr[ETHER_ADDR_LEN]; 253 254 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ 255 sbmacdma_t sbm_rxdma; 256 int rx_hw_checksum; 257 int sbe_idx; 258}; 259 260 261/********************************************************************** 262 * Externs 263 ********************************************************************* */ 264 265/********************************************************************** 266 * Prototypes 267 ********************************************************************* */ 268 269static void sbdma_initctx(sbmacdma_t *d, 270 struct sbmac_softc *s, 271 int chan, 272 int txrx, 273 int maxdescr); 274static void sbdma_channel_start(sbmacdma_t *d, int rxtx); 275static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m); 276static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m); 277static void sbdma_emptyring(sbmacdma_t *d); 278static void sbdma_fillring(sbmacdma_t *d); 279static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d); 280static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d); 281static int sbmac_initctx(struct sbmac_softc *s); 282static void sbmac_channel_start(struct sbmac_softc *s); 283static void sbmac_channel_stop(struct sbmac_softc *s); 284static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t); 285static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff); 286/*static void sbmac_init_and_start(struct sbmac_softc *sc);*/ 287static uint64_t sbmac_addr2reg(unsigned char *ptr); 288static void sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs); 289static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); 290static void sbmac_setmulti(struct sbmac_softc *sc); 291static int sbmac_init(struct net_device *dev, int idx); 292static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed); 293static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc); 294 295static int sbmac_open(struct net_device *dev); 296static void sbmac_timer(unsigned long data); 297static void sbmac_tx_timeout (struct net_device *dev); 298static struct net_device_stats *sbmac_get_stats(struct net_device *dev); 299static void sbmac_set_rx_mode(struct net_device *dev); 300static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 301static int sbmac_close(struct net_device *dev); 302static int sbmac_mii_poll(struct sbmac_softc *s,int noisy); 303 304static void sbmac_mii_sync(struct sbmac_softc *s); 305static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt); 306static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx); 307static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx, 308 unsigned int regval); 309 310 311/********************************************************************** 312 * Globals 313 ********************************************************************* */ 314 315static uint64_t sbmac_orig_hwaddr[MAX_UNITS]; 316static uint64_t chip_revision; 317 318 319/********************************************************************** 320 * MDIO constants 321 ********************************************************************* */ 322 323#define MII_COMMAND_START 0x01 324#define MII_COMMAND_READ 0x02 325#define MII_COMMAND_WRITE 0x01 326#define MII_COMMAND_ACK 0x02 327 328#define BMCR_RESET 0x8000 329#define BMCR_LOOPBACK 0x4000 330#define BMCR_SPEED0 0x2000 331#define BMCR_ANENABLE 0x1000 332#define BMCR_POWERDOWN 0x0800 333#define BMCR_ISOLATE 0x0400 334#define BMCR_RESTARTAN 0x0200 335#define BMCR_DUPLEX 0x0100 336#define BMCR_COLTEST 0x0080 337#define BMCR_SPEED1 0x0040 338#define BMCR_SPEED1000 BMCR_SPEED1 339#define BMCR_SPEED100 BMCR_SPEED0 340#define BMCR_SPEED10 0 341 342#define BMSR_100BT4 0x8000 343#define BMSR_100BT_FDX 0x4000 344#define BMSR_100BT_HDX 0x2000 345#define BMSR_10BT_FDX 0x1000 346#define BMSR_10BT_HDX 0x0800 347#define BMSR_100BT2_FDX 0x0400 348#define BMSR_100BT2_HDX 0x0200 349#define BMSR_1000BT_XSR 0x0100 350#define BMSR_PRESUP 0x0040 351#define BMSR_ANCOMPLT 0x0020 352#define BMSR_REMFAULT 0x0010 353#define BMSR_AUTONEG 0x0008 354#define BMSR_LINKSTAT 0x0004 355#define BMSR_JABDETECT 0x0002 356#define BMSR_EXTCAPAB 0x0001 357 358#define PHYIDR1 0x2000 359#define PHYIDR2 0x5C60 360 361#define ANAR_NP 0x8000 362#define ANAR_RF 0x2000 363#define ANAR_ASYPAUSE 0x0800 364#define ANAR_PAUSE 0x0400 365#define ANAR_T4 0x0200 366#define ANAR_TXFD 0x0100 367#define ANAR_TXHD 0x0080 368#define ANAR_10FD 0x0040 369#define ANAR_10HD 0x0020 370#define ANAR_PSB 0x0001 371 372#define ANLPAR_NP 0x8000 373#define ANLPAR_ACK 0x4000 374#define ANLPAR_RF 0x2000 375#define ANLPAR_ASYPAUSE 0x0800 376#define ANLPAR_PAUSE 0x0400 377#define ANLPAR_T4 0x0200 378#define ANLPAR_TXFD 0x0100 379#define ANLPAR_TXHD 0x0080 380#define ANLPAR_10FD 0x0040 381#define ANLPAR_10HD 0x0020 382#define ANLPAR_PSB 0x0001 /* 802.3 */ 383 384#define ANER_PDF 0x0010 385#define ANER_LPNPABLE 0x0008 386#define ANER_NPABLE 0x0004 387#define ANER_PAGERX 0x0002 388#define ANER_LPANABLE 0x0001 389 390#define ANNPTR_NP 0x8000 391#define ANNPTR_MP 0x2000 392#define ANNPTR_ACK2 0x1000 393#define ANNPTR_TOGTX 0x0800 394#define ANNPTR_CODE 0x0008 395 396#define ANNPRR_NP 0x8000 397#define ANNPRR_MP 0x2000 398#define ANNPRR_ACK3 0x1000 399#define ANNPRR_TOGTX 0x0800 400#define ANNPRR_CODE 0x0008 401 402#define K1TCR_TESTMODE 0x0000 403#define K1TCR_MSMCE 0x1000 404#define K1TCR_MSCV 0x0800 405#define K1TCR_RPTR 0x0400 406#define K1TCR_1000BT_FDX 0x200 407#define K1TCR_1000BT_HDX 0x100 408 409#define K1STSR_MSMCFLT 0x8000 410#define K1STSR_MSCFGRES 0x4000 411#define K1STSR_LRSTAT 0x2000 412#define K1STSR_RRSTAT 0x1000 413#define K1STSR_LP1KFD 0x0800 414#define K1STSR_LP1KHD 0x0400 415#define K1STSR_LPASMDIR 0x0200 416 417#define K1SCR_1KX_FDX 0x8000 418#define K1SCR_1KX_HDX 0x4000 419#define K1SCR_1KT_FDX 0x2000 420#define K1SCR_1KT_HDX 0x1000 421 422#define STRAP_PHY1 0x0800 423#define STRAP_NCMODE 0x0400 424#define STRAP_MANMSCFG 0x0200 425#define STRAP_ANENABLE 0x0100 426#define STRAP_MSVAL 0x0080 427#define STRAP_1KHDXADV 0x0010 428#define STRAP_1KFDXADV 0x0008 429#define STRAP_100ADV 0x0004 430#define STRAP_SPEEDSEL 0x0000 431#define STRAP_SPEED100 0x0001 432 433#define PHYSUP_SPEED1000 0x10 434#define PHYSUP_SPEED100 0x08 435#define PHYSUP_SPEED10 0x00 436#define PHYSUP_LINKUP 0x04 437#define PHYSUP_FDX 0x02 438 439#define MII_BMCR 0x00 /* Basic mode control register (rw) */ 440#define MII_BMSR 0x01 /* Basic mode status register (ro) */ 441#define MII_K1STSR 0x0A /* 1K Status Register (ro) */ 442#define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ 443 444 445#define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */ 446 447#define ENABLE 1 448#define DISABLE 0 449 450/********************************************************************** 451 * SBMAC_MII_SYNC(s) 452 * 453 * Synchronize with the MII - send a pattern of bits to the MII 454 * that will guarantee that it is ready to accept a command. 455 * 456 * Input parameters: 457 * s - sbmac structure 458 * 459 * Return value: 460 * nothing 461 ********************************************************************* */ 462 463static void sbmac_mii_sync(struct sbmac_softc *s) 464{ 465 int cnt; 466 uint64_t bits; 467 468 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT; 469 470 SBMAC_WRITECSR(s->sbm_mdio,bits); 471 472 for (cnt = 0; cnt < 32; cnt++) { 473 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC); 474 SBMAC_WRITECSR(s->sbm_mdio,bits); 475 } 476} 477 478/********************************************************************** 479 * SBMAC_MII_SENDDATA(s,data,bitcnt) 480 * 481 * Send some bits to the MII. The bits to be sent are right- 482 * justified in the 'data' parameter. 483 * 484 * Input parameters: 485 * s - sbmac structure 486 * data - data to send 487 * bitcnt - number of bits to send 488 ********************************************************************* */ 489 490static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt) 491{ 492 int i; 493 uint64_t bits; 494 unsigned int curmask; 495 496 bits = M_MAC_MDIO_DIR_OUTPUT; 497 SBMAC_WRITECSR(s->sbm_mdio,bits); 498 499 curmask = 1 << (bitcnt - 1); 500 501 for (i = 0; i < bitcnt; i++) { 502 if (data & curmask) 503 bits |= M_MAC_MDIO_OUT; 504 else bits &= ~M_MAC_MDIO_OUT; 505 SBMAC_WRITECSR(s->sbm_mdio,bits); 506 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC); 507 SBMAC_WRITECSR(s->sbm_mdio,bits); 508 curmask >>= 1; 509 } 510} 511 512 513 514/********************************************************************** 515 * SBMAC_MII_READ(s,phyaddr,regidx) 516 * 517 * Read a PHY register. 518 * 519 * Input parameters: 520 * s - sbmac structure 521 * phyaddr - PHY's address 522 * regidx = index of register to read 523 * 524 * Return value: 525 * value read, or 0 if an error occured. 526 ********************************************************************* */ 527 528static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx) 529{ 530 int idx; 531 int error; 532 int regval; 533 534 /* 535 * Synchronize ourselves so that the PHY knows the next 536 * thing coming down is a command 537 */ 538 539 sbmac_mii_sync(s); 540 541 /* 542 * Send the data to the PHY. The sequence is 543 * a "start" command (2 bits) 544 * a "read" command (2 bits) 545 * the PHY addr (5 bits) 546 * the register index (5 bits) 547 */ 548 549 sbmac_mii_senddata(s,MII_COMMAND_START, 2); 550 sbmac_mii_senddata(s,MII_COMMAND_READ, 2); 551 sbmac_mii_senddata(s,phyaddr, 5); 552 sbmac_mii_senddata(s,regidx, 5); 553 554 /* 555 * Switch the port around without a clock transition. 556 */ 557 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT); 558 559 /* 560 * Send out a clock pulse to signal we want the status 561 */ 562 563 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | M_MAC_MDC); 564 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT); 565 566 /* 567 * If an error occured, the PHY will signal '1' back 568 */ 569 error = SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN; 570 571 /* 572 * Issue an 'idle' clock pulse, but keep the direction 573 * the same. 574 */ 575 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | M_MAC_MDC); 576 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT); 577 578 regval = 0; 579 580 for (idx = 0; idx < 16; idx++) { 581 regval <<= 1; 582 583 if (error == 0) { 584 if (SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN) 585 regval |= 1; 586 } 587 588 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | M_MAC_MDC); 589 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT); 590 } 591 592 /* Switch back to output */ 593 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT); 594 595 if (error == 0) 596 return regval; 597 return 0; 598} 599 600 601/********************************************************************** 602 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval) 603 * 604 * Write a value to a PHY register. 605 * 606 * Input parameters: 607 * s - sbmac structure 608 * phyaddr - PHY to use 609 * regidx - register within the PHY 610 * regval - data to write to register 611 * 612 * Return value: 613 * nothing 614 ********************************************************************* */ 615 616static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx, 617 unsigned int regval) 618{ 619 620 sbmac_mii_sync(s); 621 622 sbmac_mii_senddata(s,MII_COMMAND_START,2); 623 sbmac_mii_senddata(s,MII_COMMAND_WRITE,2); 624 sbmac_mii_senddata(s,phyaddr, 5); 625 sbmac_mii_senddata(s,regidx, 5); 626 sbmac_mii_senddata(s,MII_COMMAND_ACK,2); 627 sbmac_mii_senddata(s,regval,16); 628 629 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT); 630} 631 632 633 634/********************************************************************** 635 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr) 636 * 637 * Initialize a DMA channel context. Since there are potentially 638 * eight DMA channels per MAC, it's nice to do this in a standard 639 * way. 640 * 641 * Input parameters: 642 * d - sbmacdma_t structure (DMA channel context) 643 * s - sbmac_softc structure (pointer to a MAC) 644 * chan - channel number (0..1 right now) 645 * txrx - Identifies DMA_TX or DMA_RX for channel direction 646 * maxdescr - number of descriptors 647 * 648 * Return value: 649 * nothing 650 ********************************************************************* */ 651 652static void sbdma_initctx(sbmacdma_t *d, 653 struct sbmac_softc *s, 654 int chan, 655 int txrx, 656 int maxdescr) 657{ 658 /* 659 * Save away interesting stuff in the structure 660 */ 661 662 d->sbdma_eth = s; 663 d->sbdma_channel = chan; 664 d->sbdma_txdir = txrx; 665 666 667 SBMAC_WRITECSR(KSEG1ADDR( 668 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)), 0); 669 SBMAC_WRITECSR(KSEG1ADDR( 670 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)), 0); 671 SBMAC_WRITECSR(KSEG1ADDR( 672 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)), 0); 673 SBMAC_WRITECSR(KSEG1ADDR( 674 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)), 0); 675 SBMAC_WRITECSR(KSEG1ADDR( 676 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)), 0); 677 SBMAC_WRITECSR(KSEG1ADDR( 678 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)), 0); 679 SBMAC_WRITECSR(KSEG1ADDR( 680 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)), 0); 681 SBMAC_WRITECSR(KSEG1ADDR( 682 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)), 0); 683 SBMAC_WRITECSR(KSEG1ADDR( 684 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)), 0); 685 SBMAC_WRITECSR(KSEG1ADDR( 686 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)), 0); 687 SBMAC_WRITECSR(KSEG1ADDR( 688 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)), 0); 689 SBMAC_WRITECSR(KSEG1ADDR( 690 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)), 0); 691 SBMAC_WRITECSR(KSEG1ADDR( 692 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)), 0); 693 SBMAC_WRITECSR(KSEG1ADDR( 694 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)), 0); 695 SBMAC_WRITECSR(KSEG1ADDR( 696 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)), 0); 697 SBMAC_WRITECSR(KSEG1ADDR( 698 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)), 0); 699 SBMAC_WRITECSR(KSEG1ADDR( 700 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)), 0); 701 SBMAC_WRITECSR(KSEG1ADDR( 702 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)), 0); 703 SBMAC_WRITECSR(KSEG1ADDR( 704 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)), 0); 705 SBMAC_WRITECSR(KSEG1ADDR( 706 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)), 0); 707 SBMAC_WRITECSR(KSEG1ADDR( 708 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)), 0); 709 710 /* 711 * initialize register pointers 712 */ 713 714 d->sbdma_config0 = 715 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0); 716 d->sbdma_config1 = 717 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1); 718 d->sbdma_dscrbase = 719 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE); 720 d->sbdma_dscrcnt = 721 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT); 722 d->sbdma_curdscr = 723 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR); 724 725 /* 726 * Allocate memory for the ring 727 */ 728 729 d->sbdma_maxdescr = maxdescr; 730 731 d->sbdma_dscrtable = (sbdmadscr_t *) 732 kmalloc(d->sbdma_maxdescr*sizeof(sbdmadscr_t), GFP_KERNEL); 733 734 memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 735 736 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; 737 738 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable); 739 740 /* 741 * And context table 742 */ 743 744 d->sbdma_ctxtable = (struct sk_buff **) 745 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL); 746 747 memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *)); 748 749#ifdef CONFIG_SBMAC_COALESCE 750 /* 751 * Setup Rx DMA coalescing defaults 752 */ 753 754 if ( txrx == DMA_RX ) { 755 if ( int_pktcnt ) { 756 d->sbdma_int_pktcnt = int_pktcnt; 757 } 758 else { 759 d->sbdma_int_pktcnt = 1; 760 } 761 762 if ( int_timeout ) { 763 d->sbdma_int_timeout = int_timeout; 764 } 765 else { 766 d->sbdma_int_timeout = 0; 767 } 768 } 769 else { 770 d->sbdma_int_pktcnt = 0; 771 d->sbdma_int_timeout = 0; 772 } 773#endif 774 775} 776 777/********************************************************************** 778 * SBDMA_CHANNEL_START(d) 779 * 780 * Initialize the hardware registers for a DMA channel. 781 * 782 * Input parameters: 783 * d - DMA channel to init (context must be previously init'd 784 * rxtx - DMA_RX or DMA_TX depending on what type of channel 785 * 786 * Return value: 787 * nothing 788 ********************************************************************* */ 789 790static void sbdma_channel_start(sbmacdma_t *d, int rxtx ) 791{ 792 /* 793 * Turn on the DMA channel 794 */ 795 796#ifdef CONFIG_SBMAC_COALESCE 797 if (rxtx == DMA_RX) { 798 SBMAC_WRITECSR(d->sbdma_config1, 799 V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) | 800 0); 801 SBMAC_WRITECSR(d->sbdma_config0, 802 M_DMA_EOP_INT_EN | 803 V_DMA_RINGSZ(d->sbdma_maxdescr) | 804 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) | 805 0); 806 } 807 else { 808 SBMAC_WRITECSR(d->sbdma_config1,0); 809 SBMAC_WRITECSR(d->sbdma_config0, 810 V_DMA_RINGSZ(d->sbdma_maxdescr) | 811 0); 812 } 813#else 814 SBMAC_WRITECSR(d->sbdma_config1,0); 815 SBMAC_WRITECSR(d->sbdma_config0, 816 V_DMA_RINGSZ(d->sbdma_maxdescr) | 817 0); 818#endif 819 820 821 SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys); 822 823 /* 824 * Initialize ring pointers 825 */ 826 827 d->sbdma_addptr = d->sbdma_dscrtable; 828 d->sbdma_remptr = d->sbdma_dscrtable; 829} 830 831/********************************************************************** 832 * SBDMA_CHANNEL_STOP(d) 833 * 834 * Initialize the hardware registers for a DMA channel. 835 * 836 * Input parameters: 837 * d - DMA channel to init (context must be previously init'd 838 * 839 * Return value: 840 * nothing 841 ********************************************************************* */ 842 843static void sbdma_channel_stop(sbmacdma_t *d) 844{ 845 /* 846 * Turn off the DMA channel 847 */ 848 849 SBMAC_WRITECSR(d->sbdma_config1,0); 850 851 SBMAC_WRITECSR(d->sbdma_dscrbase,0); 852 853 SBMAC_WRITECSR(d->sbdma_config0,0); 854 855 /* 856 * Zero ring pointers 857 */ 858 859 d->sbdma_addptr = 0; 860 d->sbdma_remptr = 0; 861} 862 863static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset) 864{ 865 unsigned long addr; 866 unsigned long newaddr; 867 868 addr = (unsigned long) skb->data; 869 870 newaddr = (addr + power2 - 1) & ~(power2 - 1); 871 872 skb_reserve(skb,newaddr-addr+offset); 873} 874 875 876/********************************************************************** 877 * SBDMA_ADD_RCVBUFFER(d,sb) 878 * 879 * Add a buffer to the specified DMA channel. For receive channels, 880 * this queues a buffer for inbound packets. 881 * 882 * Input parameters: 883 * d - DMA channel descriptor 884 * sb - sk_buff to add, or NULL if we should allocate one 885 * 886 * Return value: 887 * 0 if buffer could not be added (ring is full) 888 * 1 if buffer added successfully 889 ********************************************************************* */ 890 891 892static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb) 893{ 894 sbdmadscr_t *dsc; 895 sbdmadscr_t *nextdsc; 896 struct sk_buff *sb_new = NULL; 897 int pktsize = ENET_PACKET_SIZE; 898 899 /* get pointer to our current place in the ring */ 900 901 dsc = d->sbdma_addptr; 902 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 903 904 /* 905 * figure out if the ring is full - if the next descriptor 906 * is the same as the one that we're going to remove from 907 * the ring, the ring is full 908 */ 909 910 if (nextdsc == d->sbdma_remptr) { 911 return -ENOSPC; 912 } 913 914 /* 915 * Allocate a sk_buff if we don't already have one. 916 * If we do have an sk_buff, reset it so that it's empty. 917 * 918 * Note: sk_buffs don't seem to be guaranteed to have any sort 919 * of alignment when they are allocated. Therefore, allocate enough 920 * extra space to make sure that: 921 * 922 * 1. the data does not start in the middle of a cache line. 923 * 2. The data does not end in the middle of a cache line 924 * 3. The buffer can be aligned such that the IP addresses are 925 * naturally aligned. 926 * 927 * Remember, the SB1250's MAC writes whole cache lines at a time, 928 * without reading the old contents first. So, if the sk_buff's 929 * data portion starts in the middle of a cache line, the SB1250 930 * DMA will trash the beginning (and ending) portions. 931 */ 932 933 if (sb == NULL) { 934 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN); 935 if (sb_new == NULL) { 936 printk(KERN_INFO "%s: sk_buff allocation failed\n", 937 d->sbdma_eth->sbm_dev->name); 938 return -ENOBUFS; 939 } 940 941 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN); 942 943 /* mark skbuff owned by our device */ 944 sb_new->dev = d->sbdma_eth->sbm_dev; 945 } 946 else { 947 sb_new = sb; 948 /* 949 * nothing special to reinit buffer, it's already aligned 950 * and sb->tail already points to a good place. 951 */ 952 } 953 954 /* 955 * fill in the descriptor 956 */ 957 958#ifdef CONFIG_SBMAC_COALESCE 959 /* 960 * Do not interrupt per DMA transfer. 961 */ 962 dsc->dscr_a = virt_to_phys(sb_new->tail) | 963 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 964 0; 965#else 966 dsc->dscr_a = virt_to_phys(sb_new->tail) | 967 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 968 M_DMA_DSCRA_INTERRUPT; 969#endif 970 971 /* receiving: no options */ 972 dsc->dscr_b = 0; 973 974 /* 975 * fill in the context 976 */ 977 978 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; 979 980 /* 981 * point at next packet 982 */ 983 984 d->sbdma_addptr = nextdsc; 985 986 /* 987 * Give the buffer to the DMA engine. 988 */ 989 990 SBMAC_WRITECSR(d->sbdma_dscrcnt,1); 991 992 return 0; /* we did it */ 993} 994 995/********************************************************************** 996 * SBDMA_ADD_TXBUFFER(d,sb) 997 * 998 * Add a transmit buffer to the specified DMA channel, causing a 999 * transmit to start. 1000 * 1001 * Input parameters: 1002 * d - DMA channel descriptor 1003 * sb - sk_buff to add 1004 * 1005 * Return value: 1006 * 0 transmit queued successfully 1007 * otherwise error code 1008 ********************************************************************* */ 1009 1010 1011static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb) 1012{ 1013 sbdmadscr_t *dsc; 1014 sbdmadscr_t *nextdsc; 1015 uint64_t phys; 1016 uint64_t ncb; 1017 int length; 1018 1019 /* get pointer to our current place in the ring */ 1020 1021 dsc = d->sbdma_addptr; 1022 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 1023 1024 /* 1025 * figure out if the ring is full - if the next descriptor 1026 * is the same as the one that we're going to remove from 1027 * the ring, the ring is full 1028 */ 1029 1030 if (nextdsc == d->sbdma_remptr) { 1031 return -ENOSPC; 1032 } 1033 1034 /* 1035 * Under Linux, it's not necessary to copy/coalesce buffers 1036 * like it is on NetBSD. We think they're all contiguous, 1037 * but that may not be true for GBE. 1038 */ 1039 1040 length = sb->len; 1041 1042 /* 1043 * fill in the descriptor. Note that the number of cache 1044 * blocks in the descriptor is the number of blocks 1045 * *spanned*, so we need to add in the offset (if any) 1046 * while doing the calculation. 1047 */ 1048 1049 phys = virt_to_phys(sb->data); 1050 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1))); 1051 1052 dsc->dscr_a = phys | 1053 V_DMA_DSCRA_A_SIZE(ncb) | 1054 M_DMA_DSCRA_INTERRUPT | 1055 M_DMA_ETHTX_SOP; 1056 1057 /* transmitting: set outbound options and length */ 1058 1059 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 1060 V_DMA_DSCRB_PKT_SIZE(length); 1061 1062 /* 1063 * fill in the context 1064 */ 1065 1066 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb; 1067 1068 /* 1069 * point at next packet 1070 */ 1071 1072 d->sbdma_addptr = nextdsc; 1073 1074 /* 1075 * Give the buffer to the DMA engine. 1076 */ 1077 1078 SBMAC_WRITECSR(d->sbdma_dscrcnt,1); 1079 1080 return 0; /* we did it */ 1081} 1082 1083 1084 1085 1086/********************************************************************** 1087 * SBDMA_EMPTYRING(d) 1088 * 1089 * Free all allocated sk_buffs on the specified DMA channel; 1090 * 1091 * Input parameters: 1092 * d - DMA channel 1093 * 1094 * Return value: 1095 * nothing 1096 ********************************************************************* */ 1097 1098static void sbdma_emptyring(sbmacdma_t *d) 1099{ 1100 int idx; 1101 struct sk_buff *sb; 1102 1103 for (idx = 0; idx < d->sbdma_maxdescr; idx++) { 1104 sb = d->sbdma_ctxtable[idx]; 1105 if (sb) { 1106 dev_kfree_skb(sb); 1107 d->sbdma_ctxtable[idx] = NULL; 1108 } 1109 } 1110} 1111 1112 1113/********************************************************************** 1114 * SBDMA_FILLRING(d) 1115 * 1116 * Fill the specified DMA channel (must be receive channel) 1117 * with sk_buffs 1118 * 1119 * Input parameters: 1120 * d - DMA channel 1121 * 1122 * Return value: 1123 * nothing 1124 ********************************************************************* */ 1125 1126static void sbdma_fillring(sbmacdma_t *d) 1127{ 1128 int idx; 1129 1130 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) { 1131 if (sbdma_add_rcvbuffer(d,NULL) != 0) 1132 break; 1133 } 1134} 1135 1136 1137/********************************************************************** 1138 * SBDMA_RX_PROCESS(sc,d) 1139 * 1140 * Process "completed" receive buffers on the specified DMA channel. 1141 * Note that this isn't really ideal for priority channels, since 1142 * it processes all of the packets on a given channel before 1143 * returning. 1144 * 1145 * Input parameters: 1146 * sc - softc structure 1147 * d - DMA channel context 1148 * 1149 * Return value: 1150 * nothing 1151 ********************************************************************* */ 1152 1153static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d) 1154{ 1155 int curidx; 1156 int hwidx; 1157 sbdmadscr_t *dsc; 1158 struct sk_buff *sb; 1159 int len; 1160 1161 for (;;) { 1162 /* 1163 * figure out where we are (as an index) and where 1164 * the hardware is (also as an index) 1165 * 1166 * This could be done faster if (for example) the 1167 * descriptor table was page-aligned and contiguous in 1168 * both virtual and physical memory -- you could then 1169 * just compare the low-order bits of the virtual address 1170 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 1171 */ 1172 1173 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 1174 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 1175 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 1176 1177 /* 1178 * If they're the same, that means we've processed all 1179 * of the descriptors up to (but not including) the one that 1180 * the hardware is working on right now. 1181 */ 1182 1183 if (curidx == hwidx) 1184 break; 1185 1186 /* 1187 * Otherwise, get the packet's sk_buff ptr back 1188 */ 1189 1190 dsc = &(d->sbdma_dscrtable[curidx]); 1191 sb = d->sbdma_ctxtable[curidx]; 1192 d->sbdma_ctxtable[curidx] = NULL; 1193 1194 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; 1195 1196 /* 1197 * Check packet status. If good, process it. 1198 * If not, silently drop it and put it back on the 1199 * receive ring. 1200 */ 1201 1202 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) { 1203 1204 /* 1205 * Add a new buffer to replace the old one. If we fail 1206 * to allocate a buffer, we're going to drop this 1207 * packet and put it right back on the receive ring. 1208 */ 1209 1210 if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) { 1211 sc->sbm_stats.rx_dropped++; 1212 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */ 1213 } 1214 else { 1215 /* 1216 * Set length into the packet 1217 */ 1218 skb_put(sb,len); 1219 1220 /* 1221 * Buffer has been replaced on the receive ring. 1222 * Pass the buffer to the kernel 1223 */ 1224 sc->sbm_stats.rx_bytes += len; 1225 sc->sbm_stats.rx_packets++; 1226 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev); 1227 if (sc->rx_hw_checksum == ENABLE) { 1228 /* if the ip checksum is good indicate in skb. 1229 else set CHECKSUM_NONE as device failed to 1230 checksum the packet */ 1231 1232 if (((dsc->dscr_b) |M_DMA_ETHRX_BADTCPCS) || 1233 ((dsc->dscr_a)| M_DMA_ETHRX_BADIP4CS)){ 1234 sb->ip_summed = CHECKSUM_NONE; 1235 } else { 1236 printk(KERN_DEBUG "hw checksum fail .\n"); 1237 sb->ip_summed = CHECKSUM_UNNECESSARY; 1238 } 1239 } /*rx_hw_checksum */ 1240 1241 netif_rx(sb); 1242 } 1243 } 1244 else { 1245 /* 1246 * Packet was mangled somehow. Just drop it and 1247 * put it back on the receive ring. 1248 */ 1249 sc->sbm_stats.rx_errors++; 1250 sbdma_add_rcvbuffer(d,sb); 1251 } 1252 1253 1254 /* 1255 * .. and advance to the next buffer. 1256 */ 1257 1258 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1259 1260 } 1261} 1262 1263 1264 1265/********************************************************************** 1266 * SBDMA_TX_PROCESS(sc,d) 1267 * 1268 * Process "completed" transmit buffers on the specified DMA channel. 1269 * This is normally called within the interrupt service routine. 1270 * Note that this isn't really ideal for priority channels, since 1271 * it processes all of the packets on a given channel before 1272 * returning. 1273 * 1274 * Input parameters: 1275 * sc - softc structure 1276 * d - DMA channel context 1277 * 1278 * Return value: 1279 * nothing 1280 ********************************************************************* */ 1281 1282static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d) 1283{ 1284 int curidx; 1285 int hwidx; 1286 sbdmadscr_t *dsc; 1287 struct sk_buff *sb; 1288 unsigned long flags; 1289 1290 spin_lock_irqsave(&(sc->sbm_lock), flags); 1291 1292 for (;;) { 1293 /* 1294 * figure out where we are (as an index) and where 1295 * the hardware is (also as an index) 1296 * 1297 * This could be done faster if (for example) the 1298 * descriptor table was page-aligned and contiguous in 1299 * both virtual and physical memory -- you could then 1300 * just compare the low-order bits of the virtual address 1301 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 1302 */ 1303 1304 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 1305 { 1306 1307 uint64_t tmp = SBMAC_READCSR(d->sbdma_curdscr); 1308 if (!tmp) { 1309 break; 1310 } 1311 hwidx = (int) (((tmp & M_DMA_CURDSCR_ADDR) - 1312 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 1313 } 1314 /* 1315 * If they're the same, that means we've processed all 1316 * of the descriptors up to (but not including) the one that 1317 * the hardware is working on right now. 1318 */ 1319 1320 if (curidx == hwidx) 1321 break; 1322 1323 /* 1324 * Otherwise, get the packet's sk_buff ptr back 1325 */ 1326 1327 dsc = &(d->sbdma_dscrtable[curidx]); 1328 sb = d->sbdma_ctxtable[curidx]; 1329 d->sbdma_ctxtable[curidx] = NULL; 1330 1331 /* 1332 * Stats 1333 */ 1334 1335 sc->sbm_stats.tx_bytes += sb->len; 1336 sc->sbm_stats.tx_packets++; 1337 1338 /* 1339 * for transmits, we just free buffers. 1340 */ 1341 1342 dev_kfree_skb_irq(sb); 1343 1344 /* 1345 * .. and advance to the next buffer. 1346 */ 1347 1348 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1349 1350 } 1351 1352 /* 1353 * Decide if we should wake up the protocol or not. 1354 * Other drivers seem to do this when we reach a low 1355 * watermark on the transmit queue. 1356 */ 1357 1358 netif_wake_queue(d->sbdma_eth->sbm_dev); 1359 1360 spin_unlock_irqrestore(&(sc->sbm_lock), flags); 1361 1362} 1363 1364 1365 1366/********************************************************************** 1367 * SBMAC_INITCTX(s) 1368 * 1369 * Initialize an Ethernet context structure - this is called 1370 * once per MAC on the 1250. Memory is allocated here, so don't 1371 * call it again from inside the ioctl routines that bring the 1372 * interface up/down 1373 * 1374 * Input parameters: 1375 * s - sbmac context structure 1376 * 1377 * Return value: 1378 * 0 1379 ********************************************************************* */ 1380 1381static int sbmac_initctx(struct sbmac_softc *s) 1382{ 1383 1384 /* 1385 * figure out the addresses of some ports 1386 */ 1387 1388 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE; 1389 s->sbm_maccfg = s->sbm_base + R_MAC_CFG; 1390 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG; 1391 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG; 1392 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG; 1393 s->sbm_isr = s->sbm_base + R_MAC_STATUS; 1394 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK; 1395 s->sbm_mdio = s->sbm_base + R_MAC_MDIO; 1396 1397 s->sbm_phys[0] = 1; 1398 s->sbm_phys[1] = 0; 1399 1400 s->sbm_phy_oldbmsr = 0; 1401 s->sbm_phy_oldanlpar = 0; 1402 s->sbm_phy_oldk1stsr = 0; 1403 s->sbm_phy_oldlinkstat = 0; 1404 1405 /* 1406 * Initialize the DMA channels. Right now, only one per MAC is used 1407 * Note: Only do this _once_, as it allocates memory from the kernel! 1408 */ 1409 1410 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR); 1411 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR); 1412 1413 /* 1414 * initial state is OFF 1415 */ 1416 1417 s->sbm_state = sbmac_state_off; 1418 1419 1420 s->sbm_speed = sbmac_speed_10; 1421 s->sbm_duplex = sbmac_duplex_half; 1422 s->sbm_fc = sbmac_fc_disabled; 1423 1424 return 0; 1425} 1426 1427 1428static void sbdma_uninitctx(struct sbmacdma_s *d) 1429{ 1430 if (d->sbdma_dscrtable) { 1431 kfree(d->sbdma_dscrtable); 1432 d->sbdma_dscrtable = NULL; 1433 } 1434 1435 if (d->sbdma_ctxtable) { 1436 kfree(d->sbdma_ctxtable); 1437 d->sbdma_ctxtable = NULL; 1438 } 1439} 1440 1441 1442static void sbmac_uninitctx(struct sbmac_softc *sc) 1443{ 1444 sbdma_uninitctx(&(sc->sbm_txdma)); 1445 sbdma_uninitctx(&(sc->sbm_rxdma)); 1446} 1447 1448 1449/********************************************************************** 1450 * SBMAC_CHANNEL_START(s) 1451 * 1452 * Start packet processing on this MAC. 1453 * 1454 * Input parameters: 1455 * s - sbmac structure 1456 * 1457 * Return value: 1458 * nothing 1459 ********************************************************************* */ 1460 1461static void sbmac_channel_start(struct sbmac_softc *s) 1462{ 1463 uint64_t reg; 1464 sbmac_port_t port; 1465 uint64_t cfg,fifo,framecfg; 1466 int idx; 1467 1468 /* 1469 * Don't do this if running 1470 */ 1471 1472 if (s->sbm_state == sbmac_state_on) 1473 return; 1474 1475 /* 1476 * Bring the controller out of reset, but leave it off. 1477 */ 1478 1479 SBMAC_WRITECSR(s->sbm_macenable,0); 1480 1481 /* 1482 * Ignore all received packets 1483 */ 1484 1485 SBMAC_WRITECSR(s->sbm_rxfilter,0); 1486 1487 /* 1488 * Calculate values for various control registers. 1489 */ 1490 1491 cfg = M_MAC_RETRY_EN | 1492 M_MAC_TX_HOLD_SOP_EN | 1493 V_MAC_TX_PAUSE_CNT_16K | 1494 M_MAC_AP_STAT_EN | 1495 M_MAC_FAST_SYNC | 1496 M_MAC_SS_EN | 1497 0; 1498 1499 /* 1500 * Be sure that RD_THRSH+WR_THRSH <= 32 1501 * Use a larger RD_THRSH for gigabit 1502 */ 1503 1504 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ 1505 ((s->sbm_speed == sbmac_speed_1000) 1506 ? V_MAC_TX_RD_THRSH(28) : V_MAC_TX_RD_THRSH(4)) | 1507 V_MAC_TX_RL_THRSH(4) | 1508 V_MAC_RX_PL_THRSH(4) | 1509 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ 1510 V_MAC_RX_PL_THRSH(4) | 1511 V_MAC_RX_RL_THRSH(8) | 1512 0; 1513 1514 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | 1515 V_MAC_MAX_FRAMESZ_DEFAULT | 1516 V_MAC_BACKOFF_SEL(1); 1517 1518 1519 /* 1520 * Clear out the hash address map 1521 */ 1522 1523 port = s->sbm_base + R_MAC_HASH_BASE; 1524 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1525 SBMAC_WRITECSR(port,0); 1526 port += sizeof(uint64_t); 1527 } 1528 1529 /* 1530 * Clear out the exact-match table 1531 */ 1532 1533 port = s->sbm_base + R_MAC_ADDR_BASE; 1534 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { 1535 SBMAC_WRITECSR(port,0); 1536 port += sizeof(uint64_t); 1537 } 1538 1539 /* 1540 * Clear out the DMA Channel mapping table registers 1541 */ 1542 1543 port = s->sbm_base + R_MAC_CHUP0_BASE; 1544 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1545 SBMAC_WRITECSR(port,0); 1546 port += sizeof(uint64_t); 1547 } 1548 1549 1550 port = s->sbm_base + R_MAC_CHLO0_BASE; 1551 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1552 SBMAC_WRITECSR(port,0); 1553 port += sizeof(uint64_t); 1554 } 1555 1556 /* 1557 * Program the hardware address. It goes into the hardware-address 1558 * register as well as the first filter register. 1559 */ 1560 1561 reg = sbmac_addr2reg(s->sbm_hwaddr); 1562 1563 port = s->sbm_base + R_MAC_ADDR_BASE; 1564 SBMAC_WRITECSR(port,reg); 1565 port = s->sbm_base + R_MAC_ETHERNET_ADDR; 1566 1567#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS 1568 /* 1569 * Pass1 SB1250s do not receive packets addressed to the 1570 * destination address in the R_MAC_ETHERNET_ADDR register. 1571 * Set the value to zero. 1572 */ 1573 SBMAC_WRITECSR(port,0); 1574#else 1575 SBMAC_WRITECSR(port,reg); 1576#endif 1577 1578 /* 1579 * Set the receive filter for no packets, and write values 1580 * to the various config registers 1581 */ 1582 1583 SBMAC_WRITECSR(s->sbm_rxfilter,0); 1584 SBMAC_WRITECSR(s->sbm_imr,0); 1585 SBMAC_WRITECSR(s->sbm_framecfg,framecfg); 1586 SBMAC_WRITECSR(s->sbm_fifocfg,fifo); 1587 SBMAC_WRITECSR(s->sbm_maccfg,cfg); 1588 1589 /* 1590 * Initialize DMA channels (rings should be ok now) 1591 */ 1592 1593 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX); 1594 sbdma_channel_start(&(s->sbm_txdma), DMA_TX); 1595 1596 /* 1597 * Configure the speed, duplex, and flow control 1598 */ 1599 1600 sbmac_set_speed(s,s->sbm_speed); 1601 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc); 1602 1603 /* 1604 * Fill the receive ring 1605 */ 1606 1607 sbdma_fillring(&(s->sbm_rxdma)); 1608 1609 /* 1610 * Turn on the rest of the bits in the enable register 1611 */ 1612 1613 SBMAC_WRITECSR(s->sbm_macenable, 1614 M_MAC_RXDMA_EN0 | 1615 M_MAC_TXDMA_EN0 | 1616 M_MAC_RX_ENABLE | 1617 M_MAC_TX_ENABLE); 1618 1619 1620 1621 1622#ifdef CONFIG_SBMAC_COALESCE 1623 /* 1624 * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0 1625 */ 1626 SBMAC_WRITECSR(s->sbm_imr, 1627 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1628 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0)); 1629#else 1630 /* 1631 * Accept any kind of interrupt on TX and RX DMA channel 0 1632 */ 1633 SBMAC_WRITECSR(s->sbm_imr, 1634 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1635 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)); 1636#endif 1637 1638 /* 1639 * Enable receiving unicasts and broadcasts 1640 */ 1641 1642 SBMAC_WRITECSR(s->sbm_rxfilter,M_MAC_UCAST_EN | M_MAC_BCAST_EN); 1643 1644 /* 1645 * we're running now. 1646 */ 1647 1648 s->sbm_state = sbmac_state_on; 1649 1650 /* 1651 * Program multicast addresses 1652 */ 1653 1654 sbmac_setmulti(s); 1655 1656 /* 1657 * If channel was in promiscuous mode before, turn that on 1658 */ 1659 1660 if (s->sbm_devflags & IFF_PROMISC) { 1661 sbmac_promiscuous_mode(s,1); 1662 } 1663 1664} 1665 1666 1667/********************************************************************** 1668 * SBMAC_CHANNEL_STOP(s) 1669 * 1670 * Stop packet processing on this MAC. 1671 * 1672 * Input parameters: 1673 * s - sbmac structure 1674 * 1675 * Return value: 1676 * nothing 1677 ********************************************************************* */ 1678 1679static void sbmac_channel_stop(struct sbmac_softc *s) 1680{ 1681 /* don't do this if already stopped */ 1682 1683 if (s->sbm_state == sbmac_state_off) 1684 return; 1685 1686 /* don't accept any packets, disable all interrupts */ 1687 1688 SBMAC_WRITECSR(s->sbm_rxfilter,0); 1689 SBMAC_WRITECSR(s->sbm_imr,0); 1690 1691 /* Turn off ticker */ 1692 1693 1694 /* turn off receiver and transmitter */ 1695 1696 SBMAC_WRITECSR(s->sbm_macenable,0); 1697 1698 /* We're stopped now. */ 1699 1700 s->sbm_state = sbmac_state_off; 1701 1702 /* 1703 * Stop DMA channels (rings should be ok now) 1704 */ 1705 1706 sbdma_channel_stop(&(s->sbm_rxdma)); 1707 sbdma_channel_stop(&(s->sbm_txdma)); 1708 1709 /* Empty the receive and transmit rings */ 1710 1711 sbdma_emptyring(&(s->sbm_rxdma)); 1712 sbdma_emptyring(&(s->sbm_txdma)); 1713 1714} 1715 1716/********************************************************************** 1717 * SBMAC_SET_CHANNEL_STATE(state) 1718 * 1719 * Set the channel's state ON or OFF 1720 * 1721 * Input parameters: 1722 * state - new state 1723 * 1724 * Return value: 1725 * old state 1726 ********************************************************************* */ 1727static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc, 1728 sbmac_state_t state) 1729{ 1730 sbmac_state_t oldstate = sc->sbm_state; 1731 1732 /* 1733 * If same as previous state, return 1734 */ 1735 1736 if (state == oldstate) { 1737 return oldstate; 1738 } 1739 1740 /* 1741 * If new state is ON, turn channel on 1742 */ 1743 1744 if (state == sbmac_state_on) { 1745 sbmac_channel_start(sc); 1746 } 1747 else { 1748 sbmac_channel_stop(sc); 1749 } 1750 1751 /* 1752 * Return previous state 1753 */ 1754 1755 return oldstate; 1756} 1757 1758 1759/********************************************************************** 1760 * SBMAC_PROMISCUOUS_MODE(sc,onoff) 1761 * 1762 * Turn on or off promiscuous mode 1763 * 1764 * Input parameters: 1765 * sc - softc 1766 * onoff - 1 to turn on, 0 to turn off 1767 * 1768 * Return value: 1769 * nothing 1770 ********************************************************************* */ 1771 1772static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff) 1773{ 1774 uint64_t reg; 1775 1776 if (sc->sbm_state != sbmac_state_on) 1777 return; 1778 1779 if (onoff) { 1780 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1781 reg |= M_MAC_ALLPKT_EN; 1782 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 1783 } 1784 else { 1785 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1786 reg &= ~M_MAC_ALLPKT_EN; 1787 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 1788 } 1789} 1790 1791/********************************************************************** 1792 * SBMAC_SETIPHDR_OFFSET(sc,onoff) 1793 * 1794 * Set the iphdr offset as 15 assuming ethernet encapsulation 1795 * 1796 * Input parameters: 1797 * sc - softc 1798 * 1799 * Return value: 1800 * nothing 1801 ********************************************************************* */ 1802 1803static void sbmac_set_iphdr_offset(struct sbmac_softc *sc) 1804{ 1805 uint64_t reg; 1806 1807 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1808 reg &= ~M_MAC_IPHDR_OFFSET; 1809 /* Hard code the off set to 15 for now */ 1810 reg |= 15 << S_MAC_IPHDR_OFFSET; 1811 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 1812 1813 /* read system identification to determine revision */ 1814 if (soc_pass >= K_SYS_REVISION_PASS2) { 1815 printk(KERN_INFO "pass2 - enabling Rx rcv tcp checksum\n"); 1816 sc->rx_hw_checksum = ENABLE; 1817 } else { 1818 sc->rx_hw_checksum = DISABLE; 1819 } 1820} 1821 1822 1823 1824 1825/****************************************BMAC's address/mcast registers 1826 * 1827 * Input parameters: 1828 * ptr - pointer to 6 bytes 1829 * 1830 * Return value: 1831 * register value 1832 ********************************************************************* */ 1833 1834static uint64_t sbmac_addr2reg(unsigned char *ptr) 1835{ 1836 uint64_t reg = 0; 1837 1838 ptr += 6; 1839 1840 reg |= (uint64_t) *(--ptr); 1841 reg <<= 8; 1842 reg |= (uint64_t) *(--ptr); 1843 reg <<= 8; 1844 reg |= (uint64_t) *(--ptr); 1845 reg <<= 8; 1846 reg |= (uint64_t) *(--ptr); 1847 reg <<= 8; 1848 reg |= (uint64_t) *(--ptr); 1849 reg <<= 8; 1850 reg |= (uint64_t) *(--ptr); 1851 1852 return reg; 1853} 1854 1855 1856/********************************************************************** 1857 * SBMAC_SET_SPEED(s,speed) 1858 * 1859 * Configure LAN speed for the specified MAC. 1860 * Warning: must be called when MAC is off! 1861 * 1862 * Input parameters: 1863 * s - sbmac structure 1864 * speed - speed to set MAC to (see sbmac_speed_t enum) 1865 * 1866 * Return value: 1867 * 1 if successful 1868 * 0 indicates invalid parameters 1869 ********************************************************************* */ 1870 1871static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed) 1872{ 1873 uint64_t cfg; 1874 uint64_t framecfg; 1875 1876 /* 1877 * Save new current values 1878 */ 1879 1880 s->sbm_speed = speed; 1881 1882 if (s->sbm_state == sbmac_state_on) 1883 return 0; /* save for next restart */ 1884 1885 /* 1886 * Read current register values 1887 */ 1888 1889 cfg = SBMAC_READCSR(s->sbm_maccfg); 1890 framecfg = SBMAC_READCSR(s->sbm_framecfg); 1891 1892 /* 1893 * Mask out the stuff we want to change 1894 */ 1895 1896 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); 1897 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | 1898 M_MAC_SLOT_SIZE); 1899 1900 /* 1901 * Now add in the new bits 1902 */ 1903 1904 switch (speed) { 1905 case sbmac_speed_10: 1906 framecfg |= V_MAC_IFG_RX_10 | 1907 V_MAC_IFG_TX_10 | 1908 K_MAC_IFG_THRSH_10 | 1909 V_MAC_SLOT_SIZE_10; 1910 cfg |= V_MAC_SPEED_SEL_10MBPS; 1911 break; 1912 1913 case sbmac_speed_100: 1914 framecfg |= V_MAC_IFG_RX_100 | 1915 V_MAC_IFG_TX_100 | 1916 V_MAC_IFG_THRSH_100 | 1917 V_MAC_SLOT_SIZE_100; 1918 cfg |= V_MAC_SPEED_SEL_100MBPS ; 1919 break; 1920 1921 case sbmac_speed_1000: 1922 framecfg |= V_MAC_IFG_RX_1000 | 1923 V_MAC_IFG_TX_1000 | 1924 V_MAC_IFG_THRSH_1000 | 1925 V_MAC_SLOT_SIZE_1000; 1926 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; 1927 break; 1928 1929 case sbmac_speed_auto: 1930 /* fall through */ 1931 default: 1932 return 0; 1933 } 1934 1935 /* 1936 * Send the bits back to the hardware 1937 */ 1938 1939 SBMAC_WRITECSR(s->sbm_framecfg,framecfg); 1940 SBMAC_WRITECSR(s->sbm_maccfg,cfg); 1941 1942 return 1; 1943 1944} 1945 1946/********************************************************************** 1947 * SBMAC_SET_DUPLEX(s,duplex,fc) 1948 * 1949 * Set Ethernet duplex and flow control options for this MAC 1950 * Warning: must be called when MAC is off! 1951 * 1952 * Input parameters: 1953 * s - sbmac structure 1954 * duplex - duplex setting (see sbmac_duplex_t) 1955 * fc - flow control setting (see sbmac_fc_t) 1956 * 1957 * Return value: 1958 * 1 if ok 1959 * 0 if an invalid parameter combination was specified 1960 ********************************************************************* */ 1961 1962static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc) 1963{ 1964 uint64_t cfg; 1965 1966 /* 1967 * Save new current values 1968 */ 1969 1970 s->sbm_duplex = duplex; 1971 s->sbm_fc = fc; 1972 1973 if (s->sbm_state == sbmac_state_on) 1974 return 0; /* save for next restart */ 1975 1976 /* 1977 * Read current register values 1978 */ 1979 1980 cfg = SBMAC_READCSR(s->sbm_maccfg); 1981 1982 /* 1983 * Mask off the stuff we're about to change 1984 */ 1985 1986 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); 1987 1988 1989 switch (duplex) { 1990 case sbmac_duplex_half: 1991 switch (fc) { 1992 case sbmac_fc_disabled: 1993 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; 1994 break; 1995 1996 case sbmac_fc_collision: 1997 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; 1998 break; 1999 2000 case sbmac_fc_carrier: 2001 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; 2002 break; 2003 2004 case sbmac_fc_auto: 2005 /* fall through */ 2006 case sbmac_fc_frame: /* not valid in half duplex */ 2007 default: /* invalid selection */ 2008 return 0; 2009 } 2010 break; 2011 2012 case sbmac_duplex_full: 2013 switch (fc) { 2014 case sbmac_fc_disabled: 2015 cfg |= V_MAC_FC_CMD_DISABLED; 2016 break; 2017 2018 case sbmac_fc_frame: 2019 cfg |= V_MAC_FC_CMD_ENABLED; 2020 break; 2021 2022 case sbmac_fc_collision: /* not valid in full duplex */ 2023 case sbmac_fc_carrier: /* not valid in full duplex */ 2024 case sbmac_fc_auto: 2025 /* fall through */ 2026 default: 2027 return 0; 2028 } 2029 break; 2030 case sbmac_duplex_auto: 2031 break; 2032 } 2033 2034 /* 2035 * Send the bits back to the hardware 2036 */ 2037 2038 SBMAC_WRITECSR(s->sbm_maccfg,cfg); 2039 2040 return 1; 2041} 2042 2043 2044 2045 2046/********************************************************************** 2047 * SBMAC_INTR() 2048 * 2049 * Interrupt handler for MAC interrupts 2050 * 2051 * Input parameters: 2052 * MAC structure 2053 * 2054 * Return value: 2055 * nothing 2056 ********************************************************************* */ 2057static void sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs) 2058{ 2059 struct net_device *dev = (struct net_device *) dev_instance; 2060 struct sbmac_softc *sc = (struct sbmac_softc *) (dev->priv); 2061 uint64_t isr; 2062 2063 for (;;) { 2064 2065 /* 2066 * Read the ISR (this clears the bits in the real 2067 * register, except for counter addr) 2068 */ 2069 2070 isr = SBMAC_READCSR(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR; 2071 2072 if (isr == 0) 2073 break; 2074 2075 /* 2076 * Transmits on channel 0 2077 */ 2078 2079 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) { 2080 sbdma_tx_process(sc,&(sc->sbm_txdma)); 2081 } 2082 2083 /* 2084 * Receives on channel 0 2085 */ 2086 2087 /* 2088 * It's important to test all the bits (or at least the 2089 * EOP_SEEN bit) when deciding to do the RX process 2090 * particularly when coalescing, to make sure we 2091 * take care of the following: 2092 * 2093 * If you have some packets waiting (have been received 2094 * but no interrupt) and get a TX interrupt before 2095 * the RX timer or counter expires, reading the ISR 2096 * above will clear the timer and counter, and you 2097 * won't get another interrupt until a packet shows 2098 * up to start the timer again. Testing 2099 * EOP_SEEN here takes care of this case. 2100 * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0) 2101 */ 2102 2103 2104 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) { 2105 sbdma_rx_process(sc,&(sc->sbm_rxdma)); 2106 } 2107 } 2108 2109} 2110 2111 2112/********************************************************************** 2113 * SBMAC_START_TX(skb,dev) 2114 * 2115 * Start output on the specified interface. Basically, we 2116 * queue as many buffers as we can until the ring fills up, or 2117 * we run off the end of the queue, whichever comes first. 2118 * 2119 * Input parameters: 2120 * 2121 * 2122 * Return value: 2123 * nothing 2124 ********************************************************************* */ 2125static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev) 2126{ 2127 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv; 2128 2129 /* lock eth irq */ 2130 spin_lock_irq (&sc->sbm_lock); 2131 2132 /* 2133 * Put the buffer on the transmit ring. If we 2134 * don't have room, stop the queue. 2135 */ 2136 2137 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) { 2138 netif_stop_queue(dev); 2139 spin_unlock_irq(&sc->sbm_lock); 2140 2141 return 1; 2142 } 2143 2144 dev->trans_start = jiffies; 2145 2146 spin_unlock_irq (&sc->sbm_lock); 2147 2148 return 0; 2149} 2150 2151/********************************************************************** 2152 * SBMAC_SETMULTI(sc) 2153 * 2154 * Reprogram the multicast table into the hardware, given 2155 * the list of multicasts associated with the interface 2156 * structure. 2157 * 2158 * Input parameters: 2159 * sc - softc 2160 * 2161 * Return value: 2162 * nothing 2163 ********************************************************************* */ 2164 2165static void sbmac_setmulti(struct sbmac_softc *sc) 2166{ 2167 uint64_t reg; 2168 sbmac_port_t port; 2169 int idx; 2170 struct dev_mc_list *mclist; 2171 struct net_device *dev = sc->sbm_dev; 2172 2173 /* 2174 * Clear out entire multicast table. We do this by nuking 2175 * the entire hash table and all the direct matches except 2176 * the first one, which is used for our station address 2177 */ 2178 2179 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { 2180 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t)); 2181 SBMAC_WRITECSR(port,0); 2182 } 2183 2184 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 2185 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t)); 2186 SBMAC_WRITECSR(port,0); 2187 } 2188 2189 /* 2190 * Clear the filter to say we don't want any multicasts. 2191 */ 2192 2193 reg = SBMAC_READCSR(sc->sbm_rxfilter); 2194 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); 2195 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 2196 2197 if (dev->flags & IFF_ALLMULTI) { 2198 /* 2199 * Enable ALL multicasts. Do this by inverting the 2200 * multicast enable bit. 2201 */ 2202 reg = SBMAC_READCSR(sc->sbm_rxfilter); 2203 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); 2204 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 2205 return; 2206 } 2207 2208 2209 /* 2210 * Progam new multicast entries. For now, only use the 2211 * perfect filter. In the future we'll need to use the 2212 * hash filter if the perfect filter overflows 2213 */ 2214 2215 2216 idx = 1; /* skip station address */ 2217 mclist = dev->mc_list; 2218 while (mclist && (idx < MAC_ADDR_COUNT)) { 2219 reg = sbmac_addr2reg(mclist->dmi_addr); 2220 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t)); 2221 SBMAC_WRITECSR(port,reg); 2222 idx++; 2223 mclist = mclist->next; 2224 } 2225 2226 /* 2227 * Enable the "accept multicast bits" if we programmed at least one 2228 * multicast. 2229 */ 2230 2231 if (idx > 1) { 2232 reg = SBMAC_READCSR(sc->sbm_rxfilter); 2233 reg |= M_MAC_MCAST_EN; 2234 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 2235 } 2236} 2237 2238 2239 2240#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) 2241/********************************************************************** 2242 * SBMAC_PARSE_XDIGIT(str) 2243 * 2244 * Parse a hex digit, returning its value 2245 * 2246 * Input parameters: 2247 * str - character 2248 * 2249 * Return value: 2250 * hex value, or -1 if invalid 2251 ********************************************************************* */ 2252 2253static int sbmac_parse_xdigit(char str) 2254{ 2255 int digit; 2256 2257 if ((str >= '0') && (str <= '9')) 2258 digit = str - '0'; 2259 else if ((str >= 'a') && (str <= 'f')) 2260 digit = str - 'a' + 10; 2261 else if ((str >= 'A') && (str <= 'F')) 2262 digit = str - 'A' + 10; 2263 else 2264 return -1; 2265 2266 return digit; 2267} 2268 2269/********************************************************************** 2270 * SBMAC_PARSE_HWADDR(str,hwaddr) 2271 * 2272 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte 2273 * Ethernet address. 2274 * 2275 * Input parameters: 2276 * str - string 2277 * hwaddr - pointer to hardware address 2278 * 2279 * Return value: 2280 * 0 if ok, else -1 2281 ********************************************************************* */ 2282 2283static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr) 2284{ 2285 int digit1,digit2; 2286 int idx = 6; 2287 2288 while (*str && (idx > 0)) { 2289 digit1 = sbmac_parse_xdigit(*str); 2290 if (digit1 < 0) 2291 return -1; 2292 str++; 2293 if (!*str) 2294 return -1; 2295 2296 if ((*str == ':') || (*str == '-')) { 2297 digit2 = digit1; 2298 digit1 = 0; 2299 } 2300 else { 2301 digit2 = sbmac_parse_xdigit(*str); 2302 if (digit2 < 0) 2303 return -1; 2304 str++; 2305 } 2306 2307 *hwaddr++ = (digit1 << 4) | digit2; 2308 idx--; 2309 2310 if (*str == '-') 2311 str++; 2312 if (*str == ':') 2313 str++; 2314 } 2315 return 0; 2316} 2317#endif 2318 2319static int sb1250_change_mtu(struct net_device *_dev, int new_mtu) 2320{ 2321 if (new_mtu > ENET_PACKET_SIZE) 2322 return -EINVAL; 2323 _dev->mtu = new_mtu; 2324 printk(KERN_INFO "changing the mtu to %d\n", new_mtu); 2325 return 0; 2326} 2327 2328/********************************************************************** 2329 * SBMAC_INIT(dev) 2330 * 2331 * Attach routine - init hardware and hook ourselves into linux 2332 * 2333 * Input parameters: 2334 * dev - net_device structure 2335 * 2336 * Return value: 2337 * status 2338 ********************************************************************* */ 2339 2340static int sbmac_init(struct net_device *dev, int idx) 2341{ 2342 struct sbmac_softc *sc; 2343 unsigned char *eaddr; 2344 uint64_t ea_reg; 2345 int i; 2346 2347 sc = (struct sbmac_softc *)dev->priv; 2348 2349 /* Determine controller base address */ 2350 2351 sc->sbm_base = KSEG1ADDR(dev->base_addr); 2352 sc->sbm_dev = dev; 2353 sc->sbe_idx = idx; 2354 2355 eaddr = sc->sbm_hwaddr; 2356 2357 /* 2358 * Read the ethernet address. The firwmare left this programmed 2359 * for us in the ethernet address register for each mac. 2360 */ 2361 2362 ea_reg = SBMAC_READCSR(sc->sbm_base + R_MAC_ETHERNET_ADDR); 2363 SBMAC_WRITECSR(sc->sbm_base + R_MAC_ETHERNET_ADDR, 0); 2364 for (i = 0; i < 6; i++) { 2365 eaddr[i] = (uint8_t) (ea_reg & 0xFF); 2366 ea_reg >>= 8; 2367 } 2368 2369 for (i = 0; i < 6; i++) { 2370 dev->dev_addr[i] = eaddr[i]; 2371 } 2372 2373 2374 /* 2375 * Init packet size 2376 */ 2377 2378 sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN; 2379 2380 /* 2381 * Initialize context (get pointers to registers and stuff), then 2382 * allocate the memory for the descriptor tables. 2383 */ 2384 2385 sbmac_initctx(sc); 2386 2387 2388 /* 2389 * Display Ethernet address (this is called during the config process 2390 * so we need to finish off the config message that was being displayed) 2391 */ 2392 printk(KERN_INFO 2393 "%s: SB1250 Ethernet at 0x%08lX, address: %02X-%02X-%02X-%02X-%02X-%02X\n", 2394 dev->name, dev->base_addr, 2395 eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]); 2396 2397 /* 2398 * Set up Linux device callins 2399 */ 2400 2401 spin_lock_init(&(sc->sbm_lock)); 2402 2403 ether_setup(dev); 2404 dev->open = sbmac_open; 2405 dev->hard_start_xmit = sbmac_start_tx; 2406 dev->stop = sbmac_close; 2407 dev->get_stats = sbmac_get_stats; 2408 dev->set_multicast_list = sbmac_set_rx_mode; 2409 dev->do_ioctl = sbmac_mii_ioctl; 2410 dev->tx_timeout = sbmac_tx_timeout; 2411 dev->watchdog_timeo = TX_TIMEOUT; 2412 2413 dev->change_mtu = sb1250_change_mtu; 2414 2415 if (soc_pass >= K_SYS_REVISION_PASS3) { 2416 /* In pass3 we do dumb checksum in TX */ 2417 dev->features |= NETIF_F_IP_CSUM; 2418 } 2419 2420 /* This is needed for PASS2 for Rx H/W checksum feature */ 2421 sbmac_set_iphdr_offset( sc); 2422 2423 return 0; 2424 2425} 2426 2427 2428static int sbmac_open(struct net_device *dev) 2429{ 2430 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv; 2431 2432 MOD_INC_USE_COUNT; 2433 2434 if (debug > 1) { 2435 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq); 2436 } 2437 2438 /* 2439 * map/route interrupt 2440 */ 2441 2442 if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev)) { 2443 MOD_DEC_USE_COUNT; 2444 return -EBUSY; 2445 } 2446 2447 /* 2448 * Configure default speed 2449 */ 2450 2451 sbmac_mii_poll(sc,1); 2452 2453 /* 2454 * Turn on the channel 2455 */ 2456 2457 sbmac_set_channel_state(sc,sbmac_state_on); 2458 2459 2460 if (dev->if_port == 0) 2461 dev->if_port = 0; 2462 2463 netif_start_queue(dev); 2464 2465 sbmac_set_rx_mode(dev); 2466 2467 /* Set the timer to check for link beat. */ 2468 init_timer(&sc->sbm_timer); 2469 sc->sbm_timer.expires = jiffies + 2; 2470 sc->sbm_timer.data = (unsigned long)dev; 2471 sc->sbm_timer.function = &sbmac_timer; 2472 add_timer(&sc->sbm_timer); 2473 2474 return 0; 2475} 2476 2477 2478 2479static int sbmac_mii_poll(struct sbmac_softc *s,int noisy) 2480{ 2481 int bmsr,bmcr,k1stsr,anlpar; 2482 int chg; 2483 char buffer[100]; 2484 char *p = buffer; 2485 2486 /* Read the mode status and mode control registers. */ 2487 bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR); 2488 bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR); 2489 2490 /* get the link partner status */ 2491 anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR); 2492 2493 /* if supported, read the 1000baseT register */ 2494 if (bmsr & BMSR_1000BT_XSR) { 2495 k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR); 2496 } 2497 else { 2498 k1stsr = 0; 2499 } 2500 2501 chg = 0; 2502 2503 if ((bmsr & BMSR_LINKSTAT) == 0) { 2504 /* 2505 * If link status is down, clear out old info so that when 2506 * it comes back up it will force us to reconfigure speed 2507 */ 2508 s->sbm_phy_oldbmsr = 0; 2509 s->sbm_phy_oldanlpar = 0; 2510 s->sbm_phy_oldk1stsr = 0; 2511 return 0; 2512 } 2513 2514 if ((s->sbm_phy_oldbmsr != bmsr) || 2515 (s->sbm_phy_oldanlpar != anlpar) || 2516 (s->sbm_phy_oldk1stsr != k1stsr)) { 2517 if (debug > 1) { 2518 printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n", 2519 s->sbm_dev->name, 2520 s->sbm_phy_oldbmsr,bmsr, 2521 s->sbm_phy_oldanlpar,anlpar, 2522 s->sbm_phy_oldk1stsr,k1stsr); 2523 } 2524 s->sbm_phy_oldbmsr = bmsr; 2525 s->sbm_phy_oldanlpar = anlpar; 2526 s->sbm_phy_oldk1stsr = k1stsr; 2527 chg = 1; 2528 } 2529 2530 if (chg == 0) 2531 return 0; 2532 2533 p += sprintf(p,"Link speed: "); 2534 2535 if (k1stsr & K1STSR_LP1KFD) { 2536 s->sbm_speed = sbmac_speed_1000; 2537 s->sbm_duplex = sbmac_duplex_full; 2538 s->sbm_fc = sbmac_fc_frame; 2539 p += sprintf(p,"1000BaseT FDX"); 2540 } 2541 else if (k1stsr & K1STSR_LP1KHD) { 2542 s->sbm_speed = sbmac_speed_1000; 2543 s->sbm_duplex = sbmac_duplex_half; 2544 s->sbm_fc = sbmac_fc_disabled; 2545 p += sprintf(p,"1000BaseT HDX"); 2546 } 2547 else if (anlpar & ANLPAR_TXFD) { 2548 s->sbm_speed = sbmac_speed_100; 2549 s->sbm_duplex = sbmac_duplex_full; 2550 s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled; 2551 p += sprintf(p,"100BaseT FDX"); 2552 } 2553 else if (anlpar & ANLPAR_TXHD) { 2554 s->sbm_speed = sbmac_speed_100; 2555 s->sbm_duplex = sbmac_duplex_half; 2556 s->sbm_fc = sbmac_fc_disabled; 2557 p += sprintf(p,"100BaseT HDX"); 2558 } 2559 else if (anlpar & ANLPAR_10FD) { 2560 s->sbm_speed = sbmac_speed_10; 2561 s->sbm_duplex = sbmac_duplex_full; 2562 s->sbm_fc = sbmac_fc_frame; 2563 p += sprintf(p,"10BaseT FDX"); 2564 } 2565 else if (anlpar & ANLPAR_10HD) { 2566 s->sbm_speed = sbmac_speed_10; 2567 s->sbm_duplex = sbmac_duplex_half; 2568 s->sbm_fc = sbmac_fc_collision; 2569 p += sprintf(p,"10BaseT HDX"); 2570 } 2571 else { 2572 p += sprintf(p,"Unknown"); 2573 } 2574 2575#ifdef CONFIG_NET_SB1250_MAC_QUIET 2576 noisy = 0; 2577#endif 2578 if (noisy) { 2579 printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer); 2580 } 2581 2582 return 1; 2583} 2584 2585 2586static void sbmac_timer(unsigned long data) 2587{ 2588 struct net_device *dev = (struct net_device *)data; 2589 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv; 2590 int next_tick = HZ; 2591 int mii_status; 2592 2593 spin_lock_irq (&sc->sbm_lock); 2594 2595 /* make IFF_RUNNING follow the MII status bit "Link established" */ 2596 mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR); 2597 2598 if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) { 2599 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT; 2600 if (mii_status & BMSR_LINKSTAT) { 2601 netif_carrier_on(dev); 2602 } 2603 else { 2604 netif_carrier_off(dev); 2605 } 2606 } 2607 2608 /* 2609 * Poll the PHY to see what speed we should be running at 2610 */ 2611 2612 if (sbmac_mii_poll(sc,1)) { 2613 if (sc->sbm_state != sbmac_state_off) { 2614 /* 2615 * something changed, restart the channel 2616 */ 2617 if (debug > 1) { 2618 printk("%s: restarting channel because speed changed\n", 2619 sc->sbm_dev->name); 2620 } 2621 sbmac_channel_stop(sc); 2622 sbmac_channel_start(sc); 2623 } 2624 } 2625 2626 spin_unlock_irq (&sc->sbm_lock); 2627 2628 sc->sbm_timer.expires = jiffies + next_tick; 2629 add_timer(&sc->sbm_timer); 2630} 2631 2632 2633static void sbmac_tx_timeout (struct net_device *dev) 2634{ 2635 struct sbmac_softc *sc = (struct sbmac_softc *) dev->priv; 2636 2637 spin_lock_irq (&sc->sbm_lock); 2638 2639 2640 dev->trans_start = jiffies; 2641 sc->sbm_stats.tx_errors++; 2642 2643 spin_unlock_irq (&sc->sbm_lock); 2644 2645 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name); 2646} 2647 2648 2649 2650 2651static struct net_device_stats *sbmac_get_stats(struct net_device *dev) 2652{ 2653 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv; 2654 unsigned long flags; 2655 2656 spin_lock_irqsave(&sc->sbm_lock, flags); 2657 2658 2659 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2660 2661 return &sc->sbm_stats; 2662} 2663 2664 2665 2666static void sbmac_set_rx_mode(struct net_device *dev) 2667{ 2668 unsigned long flags; 2669 int msg_flag = 0; 2670 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv; 2671 2672 spin_lock_irqsave(&sc->sbm_lock, flags); 2673 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) { 2674 /* 2675 * Promiscuous changed. 2676 */ 2677 2678 if (dev->flags & IFF_PROMISC) { 2679 /* Unconditionally log net taps. */ 2680 msg_flag = 1; 2681 sbmac_promiscuous_mode(sc,1); 2682 } 2683 else { 2684 msg_flag = 2; 2685 sbmac_promiscuous_mode(sc,0); 2686 } 2687 } 2688 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2689 2690 if (msg_flag) { 2691 printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n", dev->name,(msg_flag==1)?"en":"dis"); 2692 } 2693 2694 /* 2695 * Program the multicasts. Do this every time. 2696 */ 2697 2698 sbmac_setmulti(sc); 2699 2700} 2701 2702static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2703{ 2704 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv; 2705 u16 *data = (u16 *)&rq->ifr_data; 2706 unsigned long flags; 2707 int retval; 2708 2709 spin_lock_irqsave(&sc->sbm_lock, flags); 2710 retval = 0; 2711 2712 switch(cmd) { 2713 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */ 2714 data[0] = sc->sbm_phys[0] & 0x1f; 2715 /* Fall Through */ 2716 case SIOCDEVPRIVATE+1: /* Read the specified MII register. */ 2717 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f); 2718 break; 2719 case SIOCDEVPRIVATE+2: /* Write the specified MII register */ 2720 if (!capable(CAP_NET_ADMIN)) { 2721 retval = -EPERM; 2722 break; 2723 } 2724 if (debug > 1) { 2725 printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name, 2726 data[0],data[1],data[2]); 2727 } 2728 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]); 2729 break; 2730 default: 2731 retval = -EOPNOTSUPP; 2732 } 2733 2734 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2735 return retval; 2736} 2737 2738static int sbmac_close(struct net_device *dev) 2739{ 2740 struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv; 2741 unsigned long flags; 2742 2743 sbmac_set_channel_state(sc,sbmac_state_off); 2744 2745 del_timer_sync(&sc->sbm_timer); 2746 2747 spin_lock_irqsave(&sc->sbm_lock, flags); 2748 2749 netif_stop_queue(dev); 2750 2751 if (debug > 1) { 2752 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name); 2753 } 2754 2755 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2756 2757 /* Make sure there is no irq-handler running on a different CPU. */ 2758 synchronize_irq(); 2759 2760 free_irq(dev->irq, dev); 2761 2762 sbdma_emptyring(&(sc->sbm_txdma)); 2763 sbdma_emptyring(&(sc->sbm_rxdma)); 2764 2765 MOD_DEC_USE_COUNT; 2766 2767 return 0; 2768} 2769 2770 2771 2772#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) 2773static void 2774sbmac_setup_hwaddr(int chan,char *addr) 2775{ 2776 uint8_t eaddr[6]; 2777 uint64_t val; 2778 sbmac_port_t port; 2779 2780 port = A_MAC_CHANNEL_BASE(chan); 2781 sbmac_parse_hwaddr(addr,eaddr); 2782 val = sbmac_addr2reg(eaddr); 2783 SBMAC_WRITECSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR),val); 2784 val = SBMAC_READCSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR)); 2785} 2786#endif 2787 2788static struct net_device *dev_sbmac[MAX_UNITS] = {0,0,0}; 2789 2790static int __init 2791sbmac_init_module(void) 2792{ 2793 int idx; 2794 int macidx = 0; 2795 struct net_device *dev; 2796 sbmac_port_t port; 2797 int chip_max_units; 2798 2799 /* 2800 * For bringup when not using the firmware, we can pre-fill 2801 * the MAC addresses using the environment variables 2802 * specified in this file (or maybe from the config file?) 2803 */ 2804#ifdef SBMAC_ETH0_HWADDR 2805 sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR); 2806#endif 2807#ifdef SBMAC_ETH1_HWADDR 2808 sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR); 2809#endif 2810#ifdef SBMAC_ETH2_HWADDR 2811 sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR); 2812#endif 2813 2814 /* 2815 * Walk through the Ethernet controllers and find 2816 * those who have their MAC addresses set. 2817 */ 2818 chip_revision = SBMAC_READCSR(KSEG1ADDR(A_SCD_SYSTEM_REVISION)); 2819 switch ((int)G_SYS_PART(chip_revision)) { 2820 case 0x1150: 2821 case 0x1250: 2822 chip_max_units = 3; 2823 break; 2824 case 0x1121: 2825 case 0x1123: 2826 case 0x1124: 2827 case 0x1125: // Hybrid. 2828 chip_max_units = 2; 2829 break; 2830 default: 2831 chip_max_units = 0; 2832 break; 2833 } 2834 if (chip_max_units > MAX_UNITS) 2835 chip_max_units = MAX_UNITS; 2836 2837 for (idx = 0; idx < chip_max_units; idx++) { 2838 2839 /* 2840 * This is the base address of the MAC. 2841 */ 2842 2843 port = A_MAC_CHANNEL_BASE(idx); 2844 2845 /* 2846 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero 2847 * value for us by the firmware if we're going to use this MAC. 2848 * If we find a zero, skip this MAC. 2849 */ 2850 2851 sbmac_orig_hwaddr[idx] = SBMAC_READCSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR)); 2852 if (sbmac_orig_hwaddr[idx] == 0) { 2853 printk(KERN_DEBUG "sbmac: not configuring MAC at " 2854 "%lx\n", port); 2855 continue; 2856 } 2857 2858 /* 2859 * Okay, cool. Initialize this MAC. 2860 */ 2861 2862 dev = init_etherdev(NULL,sizeof(struct sbmac_softc)); 2863 if (!dev) 2864 return -ENOMEM; /* return ENOMEM */ 2865 2866printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port); 2867 2868 dev->irq = K_INT_MAC_0 + idx; 2869 dev->base_addr = port; 2870 dev->mem_end = 0; 2871 /*dev->init = sbmac_init;*/ 2872 sbmac_init(dev, macidx); 2873 2874 dev_sbmac[macidx] = dev; 2875 macidx++; 2876 } 2877 2878 /* 2879 * Should we care, 'macidx' is the total number of enabled MACs. 2880 */ 2881 2882 return 0; 2883} 2884 2885 2886static void __exit 2887sbmac_cleanup_module(void) 2888{ 2889 int idx; 2890 struct net_device *dev; 2891 sbmac_port_t port; 2892 for (idx = 0; idx < MAX_UNITS; idx++) { 2893 dev = dev_sbmac[idx]; 2894 if (dev == NULL) 2895 continue; 2896 if (dev->priv != NULL) { 2897 struct sbmac_softc *sc = (struct sbmac_softc *) dev->priv; 2898 2899 unregister_netdev(dev); 2900 2901 sbmac_uninitctx(sc); 2902 2903 } 2904 2905 port = A_MAC_CHANNEL_BASE(idx); 2906 SBMAC_WRITECSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR), sbmac_orig_hwaddr[idx] ); 2907 kfree(dev); 2908 dev_sbmac[idx] = NULL; 2909 } 2910} 2911 2912module_init(sbmac_init_module); 2913module_exit(sbmac_cleanup_module); 2914