1/******************************************************************************* 2 3 4 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 2 of the License, or (at your option) 9 any later version. 10 11 This program is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 59 18 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 20 The full GNU General Public License is included in this distribution in the 21 file called LICENSE. 22 23 Contact Information: 24 Linux NICS <linux.nics@intel.com> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26*******************************************************************************/ 27 28#include "e100_phy.h" 29 30void e100_handle_zlock(struct e100_private *bdp); 31 32/* 33 * Procedure: e100_mdi_write 34 * 35 * Description: This routine will write a value to the specified MII register 36 * of an external MDI compliant device (e.g. PHY 100). The 37 * command will execute in polled mode. 38 * 39 * Arguments: 40 * bdp - Ptr to this card's e100_bdconfig structure 41 * reg_addr - The MII register that we are writing to 42 * phy_addr - The MDI address of the Phy component. 43 * data - The value that we are writing to the MII register. 44 * 45 * Returns: 46 * NOTHING 47 */ 48int 49e100_mdi_write(struct e100_private *bdp, u32 reg_addr, u32 phy_addr, u16 data) 50{ 51 int e100_retry; 52 u32 temp_val; 53 unsigned int mdi_cntrl; 54 55 spin_lock_bh(&bdp->mdi_access_lock); 56 temp_val = (((u32) data) | (reg_addr << 16) | 57 (phy_addr << 21) | (MDI_WRITE << 26)); 58 writel(temp_val, &bdp->scb->scb_mdi_cntrl); 59 readw(&bdp->scb->scb_status); 60 61 /* wait 20usec before checking status */ 62 udelay(20); 63 64 /* poll for the mdi write to complete */ 65 e100_retry = E100_CMD_WAIT; 66 while ((!((mdi_cntrl = readl(&bdp->scb->scb_mdi_cntrl)) & MDI_PHY_READY)) && (e100_retry)) { 67 68 udelay(20); 69 e100_retry--; 70 } 71 spin_unlock_bh(&bdp->mdi_access_lock); 72 if (mdi_cntrl & MDI_PHY_READY) 73 return 0; 74 else { 75 printk(KERN_ERR "e100: MDI write timeout\n"); 76 return 1; 77 } 78} 79 80/* 81 * Procedure: e100_mdi_read 82 * 83 * Description: This routine will read a value from the specified MII register 84 * of an external MDI compliant device (e.g. PHY 100), and return 85 * it to the calling routine. The command will execute in polled 86 * mode. 87 * 88 * Arguments: 89 * bdp - Ptr to this card's e100_bdconfig structure 90 * reg_addr - The MII register that we are reading from 91 * phy_addr - The MDI address of the Phy component. 92 * 93 * Results: 94 * data - The value that we read from the MII register. 95 * 96 * Returns: 97 * NOTHING 98 */ 99int 100e100_mdi_read(struct e100_private *bdp, u32 reg_addr, u32 phy_addr, u16 *data) 101{ 102 int e100_retry; 103 u32 temp_val; 104 unsigned int mdi_cntrl; 105 106 spin_lock_bh(&bdp->mdi_access_lock); 107 /* Issue the read command to the MDI control register. */ 108 temp_val = ((reg_addr << 16) | (phy_addr << 21) | (MDI_READ << 26)); 109 writel(temp_val, &bdp->scb->scb_mdi_cntrl); 110 readw(&bdp->scb->scb_status); 111 112 /* wait 20usec before checking status */ 113 udelay(20); 114 115 /* poll for the mdi read to complete */ 116 e100_retry = E100_CMD_WAIT; 117 while ((!((mdi_cntrl = readl(&bdp->scb->scb_mdi_cntrl)) & MDI_PHY_READY)) && (e100_retry)) { 118 119 udelay(20); 120 e100_retry--; 121 } 122 123 spin_unlock_bh(&bdp->mdi_access_lock); 124 if (mdi_cntrl & MDI_PHY_READY) { 125 /* return the lower word */ 126 *data = (u16) mdi_cntrl; 127 return 0; 128 } 129 else { 130 printk(KERN_ERR "e100: MDI read timeout\n"); 131 return 1; 132 } 133} 134 135static unsigned char __devinit 136e100_phy_valid(struct e100_private *bdp, unsigned int phy_address) 137{ 138 u16 ctrl_reg, stat_reg; 139 140 /* Read the MDI control register */ 141 e100_mdi_read(bdp, MII_BMCR, phy_address, &ctrl_reg); 142 143 /* Read the status register twice, bacause of sticky bits */ 144 e100_mdi_read(bdp, MII_BMSR, phy_address, &stat_reg); 145 e100_mdi_read(bdp, MII_BMSR, phy_address, &stat_reg); 146 147 if ((ctrl_reg == 0xffff) || ((stat_reg == 0) && (ctrl_reg == 0))) 148 return false; 149 150 return true; 151} 152 153static void __devinit 154e100_phy_address_detect(struct e100_private *bdp) 155{ 156 unsigned int addr; 157 unsigned char valid_phy_found = false; 158 159 if (IS_NC3133(bdp)) { 160 bdp->phy_addr = 0; 161 return; 162 } 163 164 if (e100_phy_valid(bdp, PHY_DEFAULT_ADDRESS)) { 165 bdp->phy_addr = PHY_DEFAULT_ADDRESS; 166 valid_phy_found = true; 167 168 } else { 169 for (addr = MIN_PHY_ADDR; addr <= MAX_PHY_ADDR; addr++) { 170 if (e100_phy_valid(bdp, addr)) { 171 bdp->phy_addr = addr; 172 valid_phy_found = true; 173 break; 174 } 175 } 176 } 177 178 if (!valid_phy_found) { 179 bdp->phy_addr = PHY_ADDRESS_503; 180 } 181} 182 183static void __devinit 184e100_phy_id_detect(struct e100_private *bdp) 185{ 186 u16 low_id_reg, high_id_reg; 187 188 if (bdp->phy_addr == PHY_ADDRESS_503) { 189 bdp->PhyId = PHY_503; 190 return; 191 } 192 if (!(bdp->flags & IS_ICH)) { 193 if (bdp->rev_id >= D102_REV_ID) { 194 bdp->PhyId = PHY_82562ET; 195 return; 196 } 197 } 198 199 /* Read phy id from the MII register */ 200 e100_mdi_read(bdp, MII_PHYSID1, bdp->phy_addr, &low_id_reg); 201 e100_mdi_read(bdp, MII_PHYSID2, bdp->phy_addr, &high_id_reg); 202 203 bdp->PhyId = ((unsigned int) low_id_reg | 204 ((unsigned int) high_id_reg << 16)); 205} 206 207static void __devinit 208e100_phy_isolate(struct e100_private *bdp) 209{ 210 unsigned int phy_address; 211 u16 ctrl_reg; 212 213 /* Go over all phy addresses. Deisolate the selected one, and isolate 214 * all the rest */ 215 for (phy_address = 0; phy_address <= MAX_PHY_ADDR; phy_address++) { 216 if (phy_address != bdp->phy_addr) { 217 e100_mdi_write(bdp, MII_BMCR, phy_address, 218 BMCR_ISOLATE); 219 220 } else { 221 e100_mdi_read(bdp, MII_BMCR, bdp->phy_addr, &ctrl_reg); 222 ctrl_reg &= ~BMCR_ISOLATE; 223 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg); 224 } 225 226 udelay(100); 227 } 228} 229 230static unsigned char __devinit 231e100_phy_specific_setup(struct e100_private *bdp) 232{ 233 u16 misc_reg; 234 235 if (bdp->phy_addr == PHY_ADDRESS_503) { 236 switch (bdp->params.e100_speed_duplex) { 237 case E100_AUTONEG: 238 /* The adapter can't autoneg. so set to 10/HALF */ 239 printk(KERN_INFO 240 "e100: 503 serial component detected which " 241 "cannot autonegotiate\n"); 242 printk(KERN_INFO 243 "e100: speed/duplex forced to " 244 "10Mbps / Half duplex\n"); 245 bdp->params.e100_speed_duplex = E100_SPEED_10_HALF; 246 break; 247 248 case E100_SPEED_100_HALF: 249 case E100_SPEED_100_FULL: 250 printk(KERN_ERR 251 "e100: 503 serial component detected " 252 "which does not support 100Mbps\n"); 253 printk(KERN_ERR 254 "e100: Change the forced speed/duplex " 255 "to a supported setting\n"); 256 return false; 257 } 258 259 return true; 260 } 261 262 if (IS_NC3133(bdp)) { 263 u16 int_reg; 264 265 /* enable 100BASE fiber interface */ 266 e100_mdi_write(bdp, MDI_NC3133_CONFIG_REG, bdp->phy_addr, 267 MDI_NC3133_100FX_ENABLE); 268 269 if ((bdp->params.e100_speed_duplex != E100_AUTONEG) && 270 (bdp->params.e100_speed_duplex != E100_SPEED_100_FULL)) { 271 /* just inform user about 100 full */ 272 printk(KERN_ERR "e100: NC3133 NIC can only run " 273 "at 100Mbps full duplex\n"); 274 } 275 276 bdp->params.e100_speed_duplex = E100_SPEED_100_FULL; 277 278 /* enable interrupts */ 279 e100_mdi_read(bdp, MDI_NC3133_INT_ENABLE_REG, 280 bdp->phy_addr, &int_reg); 281 int_reg |= MDI_NC3133_INT_ENABLE; 282 e100_mdi_write(bdp, MDI_NC3133_INT_ENABLE_REG, 283 bdp->phy_addr, int_reg); 284 } 285 286 /* Handle the National TX */ 287 if ((bdp->PhyId & PHY_MODEL_REV_ID_MASK) == PHY_NSC_TX) { 288 e100_mdi_read(bdp, NSC_CONG_CONTROL_REG, 289 bdp->phy_addr, &misc_reg); 290 291 misc_reg |= NSC_TX_CONG_TXREADY; 292 293 /* disable the congestion control bit in the National Phy */ 294 misc_reg &= ~NSC_TX_CONG_ENABLE; 295 296 e100_mdi_write(bdp, NSC_CONG_CONTROL_REG, 297 bdp->phy_addr, misc_reg); 298 } 299 300 return true; 301} 302 303/* 304 * Procedure: e100_phy_fix_squelch 305 * 306 * Description: 307 * Help find link on certain rare scenarios. 308 * NOTE: This routine must be called once per watchdog, 309 * and *after* setting the current link state. 310 * 311 * Arguments: 312 * bdp - Ptr to this card's e100_bdconfig structure 313 * 314 * Returns: 315 * NOTHING 316 */ 317static void 318e100_phy_fix_squelch(struct e100_private *bdp) 319{ 320 if ((bdp->PhyId != PHY_82555_TX) || (bdp->flags & DF_SPEED_FORCED)) 321 return; 322 323 if (netif_carrier_ok(bdp->device)) { 324 switch (bdp->PhyState) { 325 case 0: 326 break; 327 case 1: 328 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL, 329 bdp->phy_addr, 0x0000); 330 break; 331 case 2: 332 e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR, 333 bdp->phy_addr, 0x3000); 334 break; 335 } 336 bdp->PhyState = 0; 337 bdp->PhyDelay = 0; 338 339 } else if (!bdp->PhyDelay--) { 340 switch (bdp->PhyState) { 341 case 0: 342 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL, 343 bdp->phy_addr, EXTENDED_SQUELCH_BIT); 344 bdp->PhyState = 1; 345 break; 346 case 1: 347 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL, 348 bdp->phy_addr, 0x0000); 349 e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR, 350 bdp->phy_addr, 0x2010); 351 bdp->PhyState = 2; 352 break; 353 case 2: 354 e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR, 355 bdp->phy_addr, 0x3000); 356 bdp->PhyState = 0; 357 break; 358 } 359 360 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, 361 BMCR_ANENABLE | BMCR_ANRESTART); 362 bdp->PhyDelay = 3; 363 } 364} 365 366/* 367 * Procedure: e100_fix_polarity 368 * 369 * Description: 370 * Fix for 82555 auto-polarity toggle problem. With a short cable 371 * connecting an 82555 with an 840A link partner, if the medium is noisy, 372 * the 82555 sometime thinks that the polarity might be wrong and so 373 * toggles polarity. This happens repeatedly and results in a high bit 374 * error rate. 375 * NOTE: This happens only at 10 Mbps 376 * 377 * Arguments: 378 * bdp - Ptr to this card's e100_bdconfig structure 379 * 380 * Returns: 381 * NOTHING 382 */ 383static void __devinit 384e100_fix_polarity(struct e100_private *bdp) 385{ 386 u16 status; 387 u16 errors; 388 u16 misc_reg; 389 int speed; 390 391 if ((bdp->PhyId != PHY_82555_TX) && (bdp->PhyId != PHY_82562ET) && 392 (bdp->PhyId != PHY_82562EM)) 393 return; 394 395 /* Change for 82558 enhancement */ 396 switch (E100_AUTOPOLARITY) { 397 case 0: 398 e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL, 399 bdp->phy_addr, &misc_reg); 400 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL, bdp->phy_addr, 401 (u16) (misc_reg | DISABLE_AUTO_POLARITY)); 402 break; 403 404 case 1: 405 e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL, 406 bdp->phy_addr, &misc_reg); 407 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL, bdp->phy_addr, 408 (u16) (misc_reg & ~DISABLE_AUTO_POLARITY)); 409 break; 410 411 case 2: 412 /* we do this only if link is up */ 413 if (!netif_carrier_ok(bdp->device)) { 414 break; 415 } 416 417 e100_mdi_read(bdp, PHY_82555_CSR, bdp->phy_addr, &status); 418 speed = (status & PHY_82555_SPEED_BIT) ? 100 : 10; 419 420 /* we need to do this only if speed is 10 */ 421 if (speed != 10) { 422 break; 423 } 424 425 /* see if we have any end of frame errors */ 426 e100_mdi_read(bdp, PHY_82555_EOF_COUNTER, 427 bdp->phy_addr, &errors); 428 429 /* if non-zero, wait for 100 ms before reading again */ 430 if (errors) { 431 udelay(200); 432 e100_mdi_read(bdp, PHY_82555_EOF_COUNTER, 433 bdp->phy_addr, &errors); 434 435 /* if non-zero again, we disable polarity */ 436 if (errors) { 437 e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL, 438 bdp->phy_addr, &misc_reg); 439 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL, 440 bdp->phy_addr, 441 (u16) (misc_reg | 442 DISABLE_AUTO_POLARITY)); 443 } 444 } 445 446 if (!errors) { 447 /* it is safe to read the polarity now */ 448 e100_mdi_read(bdp, PHY_82555_CSR, 449 bdp->phy_addr, &status); 450 451 /* if polarity is normal, disable polarity */ 452 if (!(status & PHY_82555_POLARITY_BIT)) { 453 e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL, 454 bdp->phy_addr, &misc_reg); 455 e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL, 456 bdp->phy_addr, 457 (u16) (misc_reg | 458 DISABLE_AUTO_POLARITY)); 459 } 460 } 461 break; 462 463 default: 464 break; 465 } 466} 467 468/* 469 * Procedure: e100_find_speed_duplex 470 * 471 * Description: This routine will figure out what line speed and duplex mode 472 * the PHY is currently using. 473 * 474 * Arguments: 475 * bdp - Ptr to this card's e100_bdconfig structure 476 * 477 * Returns: 478 * NOTHING 479 */ 480static void 481e100_find_speed_duplex(struct e100_private *bdp) 482{ 483 unsigned int PhyId; 484 u16 stat_reg, misc_reg; 485 u16 ad_reg, lp_ad_reg; 486 487 PhyId = bdp->PhyId & PHY_MODEL_REV_ID_MASK; 488 489 /* First we should check to see if we have link */ 490 /* If we don't have a link no reason to print a speed and duplex */ 491 if (!e100_update_link_state(bdp)) { 492 bdp->cur_line_speed = 0; 493 bdp->cur_dplx_mode = 0; 494 return; 495 } 496 497 /* On the 82559 and later controllers, speed/duplex is part of the * 498 * SCB. So, we save an mdi_read and get these from the SCB. * */ 499 if (bdp->rev_id >= D101MA_REV_ID) { 500 /* Read speed */ 501 if (readb(&bdp->scb->scb_ext.d101m_scb.scb_gen_stat) & BIT_1) 502 bdp->cur_line_speed = 100; 503 else 504 bdp->cur_line_speed = 10; 505 506 /* Read duplex */ 507 if (readb(&bdp->scb->scb_ext.d101m_scb.scb_gen_stat) & BIT_2) 508 bdp->cur_dplx_mode = FULL_DUPLEX; 509 else 510 bdp->cur_dplx_mode = HALF_DUPLEX; 511 512 return; 513 } 514 515 /* If this is a Phy 100, then read bits 1 and 0 of extended register 0, 516 * to get the current speed and duplex settings. */ 517 if ((PhyId == PHY_100_A) || (PhyId == PHY_100_C) || 518 (PhyId == PHY_82555_TX)) { 519 520 /* Read Phy 100 extended register 0 */ 521 e100_mdi_read(bdp, EXTENDED_REG_0, bdp->phy_addr, &misc_reg); 522 523 /* Get current speed setting */ 524 if (misc_reg & PHY_100_ER0_SPEED_INDIC) 525 bdp->cur_line_speed = 100; 526 else 527 bdp->cur_line_speed = 10; 528 529 /* Get current duplex setting -- FDX enabled if bit is set */ 530 if (misc_reg & PHY_100_ER0_FDX_INDIC) 531 bdp->cur_dplx_mode = FULL_DUPLEX; 532 else 533 bdp->cur_dplx_mode = HALF_DUPLEX; 534 535 return; 536 } 537 538 /* See if link partner is capable of Auto-Negotiation (bit 0, reg 6) */ 539 e100_mdi_read(bdp, MII_EXPANSION, bdp->phy_addr, &misc_reg); 540 541 /* See if Auto-Negotiation was complete (bit 5, reg 1) */ 542 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg); 543 544 /* If a True NWAY connection was made, then we can detect speed/dplx 545 * by ANDing our adapter's advertised abilities with our link partner's 546 * advertised ablilities, and then assuming that the highest common 547 * denominator was chosed by NWAY. */ 548 if ((misc_reg & EXPANSION_NWAY) && (stat_reg & BMSR_ANEGCOMPLETE)) { 549 550 /* Read our advertisement register */ 551 e100_mdi_read(bdp, MII_ADVERTISE, bdp->phy_addr, &ad_reg); 552 553 /* Read our link partner's advertisement register */ 554 e100_mdi_read(bdp, MII_LPA, bdp->phy_addr, &lp_ad_reg); 555 556 /* AND the two advertisement registers together, and get rid 557 * of any extraneous bits. */ 558 ad_reg &= (lp_ad_reg & NWAY_LP_ABILITY); 559 560 /* Get speed setting */ 561 if (ad_reg & 562 (ADVERTISE_100HALF | ADVERTISE_100FULL | 563 ADVERTISE_100BASE4)) 564 565 bdp->cur_line_speed = 100; 566 else 567 bdp->cur_line_speed = 10; 568 569 /* Get duplex setting -- use priority resolution algorithm */ 570 if (ad_reg & ADVERTISE_100BASE4) { 571 bdp->cur_dplx_mode = HALF_DUPLEX; 572 } else if (ad_reg & ADVERTISE_100FULL) { 573 bdp->cur_dplx_mode = FULL_DUPLEX; 574 } else if (ad_reg & ADVERTISE_100HALF) { 575 bdp->cur_dplx_mode = HALF_DUPLEX; 576 } else if (ad_reg & ADVERTISE_10FULL) { 577 bdp->cur_dplx_mode = FULL_DUPLEX; 578 } else { 579 bdp->cur_dplx_mode = HALF_DUPLEX; 580 } 581 582 return; 583 } 584 585 /* If we are connected to a dumb (non-NWAY) repeater or hub, and the 586 * line speed was determined automatically by parallel detection, then 587 * we have no way of knowing exactly what speed the PHY is set to 588 * unless that PHY has a propietary register which indicates speed in 589 * this situation. The NSC TX PHY does have such a register. Also, 590 * since NWAY didn't establish the connection, the duplex setting 591 * should HALF duplex. */ 592 bdp->cur_dplx_mode = HALF_DUPLEX; 593 594 if (PhyId == PHY_NSC_TX) { 595 /* Read register 25 to get the SPEED_10 bit */ 596 e100_mdi_read(bdp, NSC_SPEED_IND_REG, bdp->phy_addr, &misc_reg); 597 598 /* If bit 6 was set then we're at 10Mbps */ 599 if (misc_reg & NSC_TX_SPD_INDC_SPEED) 600 bdp->cur_line_speed = 10; 601 else 602 bdp->cur_line_speed = 100; 603 604 } else { 605 /* If we don't know the line speed, default to 10Mbps */ 606 bdp->cur_line_speed = 10; 607 } 608} 609 610/* 611 * Procedure: e100_force_speed_duplex 612 * 613 * Description: This routine forces line speed and duplex mode of the 614 * adapter based on the values the user has set in e100.c. 615 * 616 * Arguments: bdp - Pointer to the e100_private structure for the board 617 * 618 * Returns: void 619 * 620 */ 621void 622e100_force_speed_duplex(struct e100_private *bdp) 623{ 624 u16 control; 625 unsigned long expires; 626 627 e100_phy_reset(bdp); 628 629 bdp->flags |= DF_SPEED_FORCED; 630 631 e100_mdi_read(bdp, MII_BMCR, bdp->phy_addr, &control); 632 control &= ~BMCR_ANENABLE; 633 control &= ~BMCR_LOOPBACK; 634 635 /* Check e100.c values */ 636 switch (bdp->params.e100_speed_duplex) { 637 case E100_SPEED_10_HALF: 638 control &= ~BMCR_SPEED100; 639 control &= ~BMCR_FULLDPLX; 640 bdp->cur_line_speed = 10; 641 bdp->cur_dplx_mode = HALF_DUPLEX; 642 break; 643 644 case E100_SPEED_10_FULL: 645 control &= ~BMCR_SPEED100; 646 control |= BMCR_FULLDPLX; 647 bdp->cur_line_speed = 10; 648 bdp->cur_dplx_mode = FULL_DUPLEX; 649 break; 650 651 case E100_SPEED_100_HALF: 652 control |= BMCR_SPEED100; 653 control &= ~BMCR_FULLDPLX; 654 bdp->cur_line_speed = 100; 655 bdp->cur_dplx_mode = HALF_DUPLEX; 656 break; 657 658 case E100_SPEED_100_FULL: 659 control |= BMCR_SPEED100; 660 control |= BMCR_FULLDPLX; 661 bdp->cur_line_speed = 100; 662 bdp->cur_dplx_mode = FULL_DUPLEX; 663 break; 664 } 665 666 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, control); 667 668 /* loop must run at least once */ 669 expires = jiffies + 2 * HZ; 670 do { 671 if (e100_update_link_state(bdp) || 672 time_after(jiffies, expires)) { 673 break; 674 } else { 675 yield(); 676 } 677 678 } while (true); 679} 680 681/* 682 * Procedure: e100_set_fc 683 * 684 * Description: Checks the link's capability for flow control. 685 * 686 * Arguments: bdp - Pointer to the e100_private structure for the board 687 * 688 * Returns: void 689 * 690 */ 691static void 692e100_set_fc(struct e100_private *bdp) 693{ 694 u16 ad_reg; 695 u16 lp_ad_reg; 696 u16 exp_reg; 697 698 /* no flow control for 82557, forced links or half duplex */ 699 if (!netif_carrier_ok(bdp->device) || (bdp->flags & DF_SPEED_FORCED) || 700 (bdp->cur_dplx_mode == HALF_DUPLEX) || 701 !(bdp->flags & IS_BACHELOR)) { 702 703 bdp->flags &= ~DF_LINK_FC_CAP; 704 return; 705 } 706 707 /* See if link partner is capable of Auto-Negotiation (bit 0, reg 6) */ 708 e100_mdi_read(bdp, MII_EXPANSION, bdp->phy_addr, &exp_reg); 709 710 if (exp_reg & EXPANSION_NWAY) { 711 /* Read our advertisement register */ 712 e100_mdi_read(bdp, MII_ADVERTISE, bdp->phy_addr, &ad_reg); 713 714 /* Read our link partner's advertisement register */ 715 e100_mdi_read(bdp, MII_LPA, bdp->phy_addr, &lp_ad_reg); 716 717 ad_reg &= lp_ad_reg; /* AND the 2 ad registers */ 718 719 if (ad_reg & NWAY_AD_FC_SUPPORTED) 720 bdp->flags |= DF_LINK_FC_CAP; 721 else 722 /* If link partner is capable of autoneg, but */ 723 /* not capable of flow control, Received PAUSE */ 724 /* frames are still honored, i.e., */ 725 /* transmitted frames would be paused */ 726 /* by incoming PAUSE frames */ 727 bdp->flags |= DF_LINK_FC_TX_ONLY; 728 729 } else { 730 bdp->flags &= ~DF_LINK_FC_CAP; 731 } 732} 733 734/* 735 * Procedure: e100_phy_check 736 * 737 * Arguments: bdp - Pointer to the e100_private structure for the board 738 * 739 * Returns: true if link state was changed 740 * false otherwise 741 * 742 */ 743unsigned char 744e100_phy_check(struct e100_private *bdp) 745{ 746 unsigned char old_link; 747 unsigned char changed = false; 748 749 old_link = netif_carrier_ok(bdp->device) ? 1 : 0; 750 e100_find_speed_duplex(bdp); 751 752 if (!old_link && netif_carrier_ok(bdp->device)) { 753 e100_set_fc(bdp); 754 changed = true; 755 } 756 757 if (old_link && !netif_carrier_ok(bdp->device)) { 758 /* reset the zero lock state */ 759 bdp->zlock_state = ZLOCK_INITIAL; 760 761 // set auto lock for phy auto-negotiation on link up 762 if ((bdp->PhyId & PHY_MODEL_REV_ID_MASK) == PHY_82555_TX) 763 e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR, 764 bdp->phy_addr, 0); 765 changed = true; 766 } 767 768 e100_phy_fix_squelch(bdp); 769 e100_handle_zlock(bdp); 770 771 return changed; 772} 773 774/* 775 * Procedure: e100_auto_neg 776 * 777 * Description: This routine will start autonegotiation and wait 778 * for it to complete 779 * 780 * Arguments: 781 * bdp - pointer to this card's e100_bdconfig structure 782 * force_restart - defines if autoneg should be restarted even if it 783 * has been completed before 784 * Returns: 785 * NOTHING 786 */ 787static void 788e100_auto_neg(struct e100_private *bdp, unsigned char force_restart) 789{ 790 u16 stat_reg; 791 unsigned long expires; 792 793 bdp->flags &= ~DF_SPEED_FORCED; 794 795 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg); 796 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg); 797 798 /* if we are capable of performing autoneg then we restart if needed */ 799 if ((stat_reg != 0xFFFF) && (stat_reg & BMSR_ANEGCAPABLE)) { 800 801 if ((!force_restart) && 802 (stat_reg & BMSR_ANEGCOMPLETE)) { 803 goto exit; 804 } 805 806 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, 807 BMCR_ANENABLE | BMCR_ANRESTART); 808 809 /* wait for autoneg to complete (up to 3 seconds) */ 810 expires = jiffies + HZ * 3; 811 do { 812 /* now re-read the value. Sticky so read twice */ 813 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg); 814 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg); 815 816 if ((stat_reg & BMSR_ANEGCOMPLETE) || 817 time_after(jiffies, expires) ) { 818 goto exit; 819 } else { 820 yield(); 821 } 822 } while (true); 823 } 824 825exit: 826 e100_find_speed_duplex(bdp); 827} 828 829void 830e100_phy_set_speed_duplex(struct e100_private *bdp, unsigned char force_restart) 831{ 832 if (bdp->params.e100_speed_duplex == E100_AUTONEG) { 833 if (bdp->rev_id >= D102_REV_ID) 834 /* Enable MDI/MDI-X auto switching */ 835 e100_mdi_write(bdp, MII_NCONFIG, bdp->phy_addr, 836 MDI_MDIX_AUTO_SWITCH_ENABLE); 837 e100_auto_neg(bdp, force_restart); 838 839 } else { 840 if (bdp->rev_id >= D102_REV_ID) 841 /* Disable MDI/MDI-X auto switching */ 842 e100_mdi_write(bdp, MII_NCONFIG, bdp->phy_addr, 843 MDI_MDIX_RESET_ALL_MASK); 844 e100_force_speed_duplex(bdp); 845 } 846 847 e100_set_fc(bdp); 848} 849 850void 851e100_phy_autoneg(struct e100_private *bdp) 852{ 853 u16 ctrl_reg; 854 855 ctrl_reg = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; 856 857 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg); 858 859 udelay(100); 860} 861 862void 863e100_phy_set_loopback(struct e100_private *bdp) 864{ 865 u16 ctrl_reg; 866 ctrl_reg = BMCR_LOOPBACK; 867 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg); 868 udelay(100); 869} 870 871void 872e100_phy_reset(struct e100_private *bdp) 873{ 874 u16 ctrl_reg; 875 ctrl_reg = BMCR_RESET; 876 e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg); 877} 878 879unsigned char __devinit 880e100_phy_init(struct e100_private *bdp) 881{ 882 e100_phy_address_detect(bdp); 883 e100_phy_isolate(bdp); 884 e100_phy_id_detect(bdp); 885 886 if (!e100_phy_specific_setup(bdp)) 887 return false; 888 889 bdp->PhyState = 0; 890 bdp->PhyDelay = 0; 891 bdp->zlock_state = ZLOCK_INITIAL; 892 893 e100_phy_set_speed_duplex(bdp, false); 894 e100_fix_polarity(bdp); 895 896 return true; 897} 898 899/* 900 * Procedure: e100_get_link_state 901 * 902 * Description: This routine checks the link status of the adapter 903 * 904 * Arguments: bdp - Pointer to the e100_private structure for the board 905 * 906 * 907 * Returns: true - If a link is found 908 * false - If there is no link 909 * 910 */ 911unsigned char 912e100_get_link_state(struct e100_private *bdp) 913{ 914 unsigned char link = false; 915 u16 status; 916 917 /* Check link status */ 918 /* If the controller is a 82559 or later one, link status is available 919 * from the CSR. This avoids the mdi_read. */ 920 if (bdp->rev_id >= D101MA_REV_ID) { 921 if (readb(&bdp->scb->scb_ext.d101m_scb.scb_gen_stat) & BIT_0) { 922 link = true; 923 } else { 924 link = false; 925 } 926 927 } else { 928 /* Read the status register twice because of sticky bits */ 929 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &status); 930 e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &status); 931 932 if (status & BMSR_LSTATUS) { 933 link = true; 934 } else { 935 link = false; 936 } 937 } 938 939 return link; 940} 941 942/* 943 * Procedure: e100_update_link_state 944 * 945 * Description: This routine updates the link status of the adapter, 946 * also considering netif_running 947 * 948 * Arguments: bdp - Pointer to the e100_private structure for the board 949 * 950 * 951 * Returns: true - If a link is found 952 * false - If there is no link 953 * 954 */ 955unsigned char 956e100_update_link_state(struct e100_private *bdp) 957{ 958 unsigned char link; 959 960 /* Logical AND PHY link & netif_running */ 961 link = e100_get_link_state(bdp) && netif_running(bdp->device); 962 963 if (link) { 964 if (!netif_carrier_ok(bdp->device)) 965 netif_carrier_on(bdp->device); 966 } else { 967 if (netif_carrier_ok(bdp->device)) 968 netif_carrier_off(bdp->device); 969 } 970 971 return link; 972} 973 974/**************************************************************************\ 975 ** 976 ** PROC NAME: e100_handle_zlock 977 ** This function manages a state machine that controls 978 ** the driver's zero locking algorithm. 979 ** This function is called by e100_watchdog() every ~2 second. 980 ** States: 981 ** The current link handling state is stored in 982 ** bdp->zlock_state, and is one of: 983 ** ZLOCK_INITIAL, ZLOCK_READING, ZLOCK_SLEEPING 984 ** Detailed description of the states and the transitions 985 ** between states is found below. 986 ** Note that any time the link is down / there is a reset 987 ** state will be changed outside this function to ZLOCK_INITIAL 988 ** Algorithm: 989 ** 1. If link is up & 100 Mbps continue else stay in #1: 990 ** 2. Set 'auto lock' 991 ** 3. Read & Store 100 times 'Zero' locked in 1 sec interval 992 ** 4. If max zero read >= 0xB continue else goto 1 993 ** 5. Set most popular 'Zero' read in #3 994 ** 6. Sleep 5 minutes 995 ** 7. Read number of errors, if it is > 300 goto 2 else goto 6 996 ** Data Structures (in DRIVER_DATA): 997 ** zlock_state - current state of the algorithm 998 ** zlock_read_cnt - counts number of reads (up to 100) 999 ** zlock_read_data[i] - counts number of times 'Zero' read was i, 0 <= i <= 15 1000 ** zlock_sleep_cnt - keeps track of "sleep" time (up to 300 secs = 5 minutes) 1001 ** 1002 ** Parameters: DRIVER_DATA *bdp 1003 ** 1004 ** bdp - Pointer to HSM's adapter data space 1005 ** 1006 ** Return Value: NONE 1007 ** 1008 ** See Also: e100_watchdog() 1009 ** 1010 \**************************************************************************/ 1011void 1012e100_handle_zlock(struct e100_private *bdp) 1013{ 1014 u16 pos; 1015 u16 eq_reg; 1016 u16 err_cnt; 1017 u8 mpz; /* Most Popular Zero */ 1018 1019 switch (bdp->zlock_state) { 1020 case ZLOCK_INITIAL: 1021 1022 if (((u8) bdp->rev_id <= D102_REV_ID) || 1023 !(bdp->cur_line_speed == 100) || 1024 !netif_carrier_ok(bdp->device)) { 1025 break; 1026 } 1027 1028 /* initialize hw and sw and start reading */ 1029 e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR, 1030 bdp->phy_addr, 0); 1031 /* reset read counters: */ 1032 bdp->zlock_read_cnt = 0; 1033 for (pos = 0; pos < 16; pos++) 1034 bdp->zlock_read_data[pos] = 0; 1035 /* start reading in the next call back: */ 1036 bdp->zlock_state = ZLOCK_READING; 1037 1038 /* FALL THROUGH !! */ 1039 1040 case ZLOCK_READING: 1041 /* state: reading (100 times) zero locked in 1 sec interval 1042 * prev states: ZLOCK_INITIAL 1043 * next states: ZLOCK_INITIAL, ZLOCK_SLEEPING */ 1044 1045 e100_mdi_read(bdp, PHY_82555_MDI_EQUALIZER_CSR, 1046 bdp->phy_addr, &eq_reg); 1047 pos = (eq_reg & ZLOCK_ZERO_MASK) >> 4; 1048 bdp->zlock_read_data[pos]++; 1049 bdp->zlock_read_cnt++; 1050 1051 if (bdp->zlock_read_cnt == ZLOCK_MAX_READS) { 1052 /* check if we read a 'Zero' value of 0xB or greater */ 1053 if ((bdp->zlock_read_data[0xB]) || 1054 (bdp->zlock_read_data[0xC]) || 1055 (bdp->zlock_read_data[0xD]) || 1056 (bdp->zlock_read_data[0xE]) || 1057 (bdp->zlock_read_data[0xF])) { 1058 1059 /* we've read 'Zero' value of 0xB or greater, 1060 * find most popular 'Zero' value and lock it */ 1061 mpz = 0; 1062 /* this loop finds the most popular 'Zero': */ 1063 for (pos = 1; pos < 16; pos++) { 1064 if (bdp->zlock_read_data[pos] > 1065 bdp->zlock_read_data[mpz]) 1066 1067 mpz = pos; 1068 } 1069 /* now lock the most popular 'Zero': */ 1070 eq_reg = (ZLOCK_SET_ZERO | mpz); 1071 e100_mdi_write(bdp, 1072 PHY_82555_MDI_EQUALIZER_CSR, 1073 bdp->phy_addr, eq_reg); 1074 1075 /* sleep for 5 minutes: */ 1076 bdp->zlock_sleep_cnt = jiffies; 1077 bdp->zlock_state = ZLOCK_SLEEPING; 1078 /* we will be reading the # of errors after 5 1079 * minutes, so we need to reset the error 1080 * counters - these registers are self clearing 1081 * on read, so read them */ 1082 e100_mdi_read(bdp, PHY_82555_SYMBOL_ERR, 1083 bdp->phy_addr, &err_cnt); 1084 1085 } else { 1086 /* we did not read a 'Zero' value of 0xB or 1087 * above. go back to the start */ 1088 bdp->zlock_state = ZLOCK_INITIAL; 1089 } 1090 1091 } 1092 break; 1093 1094 case ZLOCK_SLEEPING: 1095 /* state: sleeping for 5 minutes 1096 * prev states: ZLOCK_READING 1097 * next states: ZLOCK_READING, ZLOCK_SLEEPING */ 1098 1099 /* if 5 minutes have passed: */ 1100 if ((jiffies - bdp->zlock_sleep_cnt) >= ZLOCK_MAX_SLEEP) { 1101 /* read and sum up the number of errors: */ 1102 e100_mdi_read(bdp, PHY_82555_SYMBOL_ERR, 1103 bdp->phy_addr, &err_cnt); 1104 /* if we've more than 300 errors (this number was 1105 * calculated according to the spec max allowed errors 1106 * (80 errors per 1 million frames) for 5 minutes in 1107 * 100 Mbps (or the user specified max BER number) */ 1108 if (err_cnt > bdp->params.ber) { 1109 /* start again in the next callback: */ 1110 bdp->zlock_state = ZLOCK_INITIAL; 1111 } else { 1112 /* we don't have more errors than allowed, 1113 * sleep for 5 minutes */ 1114 bdp->zlock_sleep_cnt = jiffies; 1115 } 1116 } 1117 break; 1118 1119 default: 1120 break; 1121 } 1122} 1123