Searched refs:IDENT_ADDR (Results 1 - 25 of 37) sorted by relevance

12

/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-alpha/
H A Dcore_apecs.h77 #define APECS_IOC_DCSR (IDENT_ADDR + 0x1A0000000UL)
78 #define APECS_IOC_PEAR (IDENT_ADDR + 0x1A0000020UL)
79 #define APECS_IOC_SEAR (IDENT_ADDR + 0x1A0000040UL)
80 #define APECS_IOC_DR1 (IDENT_ADDR + 0x1A0000060UL)
81 #define APECS_IOC_DR2 (IDENT_ADDR + 0x1A0000080UL)
82 #define APECS_IOC_DR3 (IDENT_ADDR + 0x1A00000A0UL)
84 #define APECS_IOC_TB1R (IDENT_ADDR + 0x1A00000C0UL)
85 #define APECS_IOC_TB2R (IDENT_ADDR + 0x1A00000E0UL)
87 #define APECS_IOC_PB1R (IDENT_ADDR + 0x1A0000100UL)
88 #define APECS_IOC_PB2R (IDENT_ADDR
[all...]
H A Dcore_lca.h61 #define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL)
62 #define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL)
63 #define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL)
64 #define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL)
65 #define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL)
66 #define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL)
67 #define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL)
68 #define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL)
69 #define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL)
70 #define LCA_MEM_BTR1 (IDENT_ADDR
[all...]
H A Dcore_cia.h73 #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
75 #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
76 #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
101 #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
106 #define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL)
107 #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
108 #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
109 #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
110 #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
120 #define CIA_IOC_CIA_DIAG (IDENT_ADDR
[all...]
H A Dcore_t2.h38 #define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
39 #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
40 #define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
41 #define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
43 #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
44 #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
45 #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
46 #define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
47 #define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
48 #define T2_PERR2 (IDENT_ADDR
[all...]
H A Djensen.h36 #define EISA_INTA (IDENT_ADDR + 0x100000000UL)
41 #define EISA_FEPROM0 (IDENT_ADDR + 0x180000000UL)
42 #define EISA_FEPROM1 (IDENT_ADDR + 0x1A0000000UL)
47 #define EISA_VL82C106 (IDENT_ADDR + 0x1C0000000UL)
52 #define EISA_HAE (IDENT_ADDR + 0x1D0000000UL)
57 #define EISA_SYSCTL (IDENT_ADDR + 0x1E0000000UL)
62 #define EISA_SPARE (IDENT_ADDR + 0x1F0000000UL)
67 #define EISA_MEM (IDENT_ADDR + 0x200000000UL)
72 #define EISA_IO (IDENT_ADDR + 0x300000000UL)
H A Dcore_polaris.h21 #define POLARIS_SPARSE_MEM_BASE (IDENT_ADDR + 0xf800000000)
22 #define POLARIS_DENSE_MEM_BASE (IDENT_ADDR + 0xf900000000)
23 #define POLARIS_SPARSE_IO_BASE (IDENT_ADDR + 0xf980000000)
24 #define POLARIS_SPARSE_CONFIG_BASE (IDENT_ADDR + 0xf9c0000000)
25 #define POLARIS_IACK_BASE (IDENT_ADDR + 0xf9f8000000)
26 #define POLARIS_DENSE_IO_BASE (IDENT_ADDR + 0xf9fc000000)
27 #define POLARIS_DENSE_CONFIG_BASE (IDENT_ADDR + 0xf9fe000000)
H A Dcore_mcpcia.h86 #define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
87 #define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
88 #define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
89 #define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
90 #define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
91 #define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
92 #define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
93 #define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
H A Dcore_irongate.h118 #define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
119 #define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
120 #define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
121 #define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
H A Dmmu_context.h231 tsk->thread.ptbr = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
244 tsk->thread.ptbr = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
H A Ddma.h92 #define ALPHA_XL_MAX_DMA_ADDRESS (IDENT_ADDR+0x3000000UL)
93 #define ALPHA_RUFFIAN_MAX_DMA_ADDRESS (IDENT_ADDR+0x1000000UL)
94 #define ALPHA_NAUTILUS_MAX_DMA_ADDRESS (IDENT_ADDR+0x1000000UL)
H A Dcore_titan.h125 #define TITAN_cchip ((titan_cchip *)(IDENT_ADDR+TI_BIAS+0x1A0000000UL))
126 #define TITAN_dchip ((titan_dchip *)(IDENT_ADDR+TI_BIAS+0x1B0000800UL))
127 #define TITAN_pachip0 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x180000000UL))
128 #define TITAN_pachip1 ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x380000000UL))
296 #define TITAN_BASE (IDENT_ADDR + TI_BIAS)
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-alpha/
H A Dcore_apecs.h77 #define APECS_IOC_DCSR (IDENT_ADDR + 0x1A0000000UL)
78 #define APECS_IOC_PEAR (IDENT_ADDR + 0x1A0000020UL)
79 #define APECS_IOC_SEAR (IDENT_ADDR + 0x1A0000040UL)
80 #define APECS_IOC_DR1 (IDENT_ADDR + 0x1A0000060UL)
81 #define APECS_IOC_DR2 (IDENT_ADDR + 0x1A0000080UL)
82 #define APECS_IOC_DR3 (IDENT_ADDR + 0x1A00000A0UL)
84 #define APECS_IOC_TB1R (IDENT_ADDR + 0x1A00000C0UL)
85 #define APECS_IOC_TB2R (IDENT_ADDR + 0x1A00000E0UL)
87 #define APECS_IOC_PB1R (IDENT_ADDR + 0x1A0000100UL)
88 #define APECS_IOC_PB2R (IDENT_ADDR
[all...]
H A Dcore_lca.h61 #define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL)
62 #define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL)
63 #define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL)
64 #define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL)
65 #define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL)
66 #define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL)
67 #define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL)
68 #define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL)
69 #define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL)
70 #define LCA_MEM_BTR1 (IDENT_ADDR
[all...]
H A Dcore_cia.h73 #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
75 #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
76 #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
101 #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
106 #define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL)
107 #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
108 #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
109 #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
110 #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
120 #define CIA_IOC_CIA_DIAG (IDENT_ADDR
[all...]
H A Dcore_t2.h38 #define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
39 #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
40 #define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
41 #define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
43 #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
44 #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
45 #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
46 #define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
47 #define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
48 #define T2_PERR2 (IDENT_ADDR
[all...]
H A Djensen.h36 #define EISA_INTA (IDENT_ADDR + 0x100000000UL)
41 #define EISA_FEPROM0 (IDENT_ADDR + 0x180000000UL)
42 #define EISA_FEPROM1 (IDENT_ADDR + 0x1A0000000UL)
47 #define EISA_VL82C106 (IDENT_ADDR + 0x1C0000000UL)
52 #define EISA_HAE (IDENT_ADDR + 0x1D0000000UL)
57 #define EISA_SYSCTL (IDENT_ADDR + 0x1E0000000UL)
62 #define EISA_SPARE (IDENT_ADDR + 0x1F0000000UL)
67 #define EISA_MEM (IDENT_ADDR + 0x200000000UL)
72 #define EISA_IO (IDENT_ADDR + 0x300000000UL)
H A Dcore_polaris.h21 #define POLARIS_SPARSE_MEM_BASE (IDENT_ADDR + 0xf800000000)
22 #define POLARIS_DENSE_MEM_BASE (IDENT_ADDR + 0xf900000000)
23 #define POLARIS_SPARSE_IO_BASE (IDENT_ADDR + 0xf980000000)
24 #define POLARIS_SPARSE_CONFIG_BASE (IDENT_ADDR + 0xf9c0000000)
25 #define POLARIS_IACK_BASE (IDENT_ADDR + 0xf9f8000000)
26 #define POLARIS_DENSE_IO_BASE (IDENT_ADDR + 0xf9fc000000)
27 #define POLARIS_DENSE_CONFIG_BASE (IDENT_ADDR + 0xf9fe000000)
H A Dcore_mcpcia.h86 #define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
87 #define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
88 #define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
89 #define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
90 #define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
91 #define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
92 #define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
93 #define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
H A Dcore_irongate.h118 #define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
119 #define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
120 #define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
121 #define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
H A Dmmu_context.h231 tsk->thread.ptbr = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
244 tsk->thread.ptbr = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
H A Ddma.h92 #define ALPHA_XL_MAX_DMA_ADDRESS (IDENT_ADDR+0x3000000UL)
93 #define ALPHA_RUFFIAN_MAX_DMA_ADDRESS (IDENT_ADDR+0x1000000UL)
94 #define ALPHA_NAUTILUS_MAX_DMA_ADDRESS (IDENT_ADDR+0x1000000UL)
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/alpha/kernel/
H A Dcore_polaris.c199 hose->dense_mem_base = POLARIS_DENSE_MEM_BASE - IDENT_ADDR;
201 hose->dense_io_base = POLARIS_DENSE_IO_BASE - IDENT_ADDR;
H A Dsys_jensen.c209 hose->sparse_mem_base = EISA_MEM - IDENT_ADDR;
211 hose->sparse_io_base = EISA_IO - IDENT_ADDR;
H A Dcore_apecs.c379 hose->sparse_mem_base = APECS_SPARSE_MEM - IDENT_ADDR;
380 hose->dense_mem_base = APECS_DENSE_MEM - IDENT_ADDR;
381 hose->sparse_io_base = APECS_IO - IDENT_ADDR;
H A Dcore_t2.c349 hose->sparse_mem_base = T2_SPARSE_MEM - IDENT_ADDR;
350 hose->dense_mem_base = T2_DENSE_MEM - IDENT_ADDR;
351 hose->sparse_io_base = T2_IO - IDENT_ADDR;

Completed in 199 milliseconds

12