Lines Matching refs:IDENT_ADDR
38 #define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
39 #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
40 #define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
41 #define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
43 #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
44 #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
45 #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
46 #define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
47 #define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
48 #define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
49 #define T2_PSCR (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
50 #define T2_HAE_1 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
51 #define T2_HAE_2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
52 #define T2_HBASE (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL)
53 #define T2_WBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL)
54 #define T2_WMASK1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL)
55 #define T2_TBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL)
56 #define T2_WBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL)
57 #define T2_WMASK2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
58 #define T2_TBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
59 #define T2_TLBBR (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
61 #define T2_HAE_3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
62 #define T2_HAE_4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
99 #define T2_CPU0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x380000000L)
100 #define T2_CPU1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x381000000L)
101 #define T2_CPU2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x382000000L)
102 #define T2_CPU3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x383000000L)
103 #define T2_MEM0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x388000000L)
104 #define T2_MEM1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x389000000L)
105 #define T2_MEM2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L)
106 #define T2_MEM3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L)