Lines Matching refs:IDENT_ADDR
73 #define CIA_IOC_CIA_REV (IDENT_ADDR + 0x8740000080UL)
75 #define CIA_IOC_PCI_LAT (IDENT_ADDR + 0x87400000C0UL)
76 #define CIA_IOC_CIA_CTRL (IDENT_ADDR + 0x8740000100UL)
101 #define CIA_IOC_CIA_CNFG (IDENT_ADDR + 0x8740000140UL)
106 #define CIA_IOC_FLASH_CTRL (IDENT_ADDR + 0x8740000200UL)
107 #define CIA_IOC_HAE_MEM (IDENT_ADDR + 0x8740000400UL)
108 #define CIA_IOC_HAE_IO (IDENT_ADDR + 0x8740000440UL)
109 #define CIA_IOC_CFG (IDENT_ADDR + 0x8740000480UL)
110 #define CIA_IOC_CACK_EN (IDENT_ADDR + 0x8740000600UL)
120 #define CIA_IOC_CIA_DIAG (IDENT_ADDR + 0x8740002000UL)
121 #define CIA_IOC_DIAG_CHECK (IDENT_ADDR + 0x8740003000UL)
126 #define CIA_IOC_PERF_MONITOR (IDENT_ADDR + 0x8740004000UL)
127 #define CIA_IOC_PERF_CONTROL (IDENT_ADDR + 0x8740004040UL)
132 #define CIA_IOC_CPU_ERR0 (IDENT_ADDR + 0x8740008000UL)
133 #define CIA_IOC_CPU_ERR1 (IDENT_ADDR + 0x8740008040UL)
134 #define CIA_IOC_CIA_ERR (IDENT_ADDR + 0x8740008200UL)
159 #define CIA_IOC_CIA_STAT (IDENT_ADDR + 0x8740008240UL)
160 #define CIA_IOC_ERR_MASK (IDENT_ADDR + 0x8740008280UL)
161 #define CIA_IOC_CIA_SYN (IDENT_ADDR + 0x8740008300UL)
162 #define CIA_IOC_MEM_ERR0 (IDENT_ADDR + 0x8740008400UL)
163 #define CIA_IOC_MEM_ERR1 (IDENT_ADDR + 0x8740008440UL)
164 #define CIA_IOC_PCI_ERR0 (IDENT_ADDR + 0x8740008800UL)
165 #define CIA_IOC_PCI_ERR1 (IDENT_ADDR + 0x8740008840UL)
166 #define CIA_IOC_PCI_ERR3 (IDENT_ADDR + 0x8740008880UL)
171 #define CIA_IOC_MCR (IDENT_ADDR + 0x8750000000UL)
172 #define CIA_IOC_MBA0 (IDENT_ADDR + 0x8750000600UL)
173 #define CIA_IOC_MBA2 (IDENT_ADDR + 0x8750000680UL)
174 #define CIA_IOC_MBA4 (IDENT_ADDR + 0x8750000700UL)
175 #define CIA_IOC_MBA6 (IDENT_ADDR + 0x8750000780UL)
176 #define CIA_IOC_MBA8 (IDENT_ADDR + 0x8750000800UL)
177 #define CIA_IOC_MBAA (IDENT_ADDR + 0x8750000880UL)
178 #define CIA_IOC_MBAC (IDENT_ADDR + 0x8750000900UL)
179 #define CIA_IOC_MBAE (IDENT_ADDR + 0x8750000980UL)
180 #define CIA_IOC_TMG0 (IDENT_ADDR + 0x8750000B00UL)
181 #define CIA_IOC_TMG1 (IDENT_ADDR + 0x8750000B40UL)
182 #define CIA_IOC_TMG2 (IDENT_ADDR + 0x8750000B80UL)
187 #define CIA_IOC_PCI_TBIA (IDENT_ADDR + 0x8760000100UL)
189 #define CIA_IOC_PCI_W0_BASE (IDENT_ADDR + 0x8760000400UL)
190 #define CIA_IOC_PCI_W0_MASK (IDENT_ADDR + 0x8760000440UL)
191 #define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
193 #define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
194 #define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)
195 #define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)
197 #define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)
198 #define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)
199 #define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)
201 #define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)
202 #define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)
203 #define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)
205 #define CIA_IOC_PCI_W_DAC (IDENT_ADDR + 0x87600007C0UL)
213 (IDENT_ADDR + 0x8760000800UL + (n)*0x40)
217 (IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
222 #define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)
223 #define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
224 #define CIA_IO (IDENT_ADDR + 0x8580000000UL)
225 #define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL)
226 #define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL)
227 #define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL)
228 #define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL)
229 #define CIA_BW_MEM (IDENT_ADDR + 0x8800000000UL)
230 #define CIA_BW_IO (IDENT_ADDR + 0x8900000000UL)
231 #define CIA_BW_CFG_0 (IDENT_ADDR + 0x8a00000000UL)
232 #define CIA_BW_CFG_1 (IDENT_ADDR + 0x8b00000000UL)
237 #define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL)
238 #define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL)
239 #define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL)
240 #define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL)
241 #define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL)
243 #define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL)
244 #define GRU_SCR (IDENT_ADDR + 0x8780000300UL)
245 #define GRU_LED (IDENT_ADDR + 0x8780000800UL)
246 #define GRU_RESET (IDENT_ADDR + 0x8780000900UL)
255 #define PYXIS_INT_REQ (IDENT_ADDR + 0x87A0000000UL)
256 #define PYXIS_INT_MASK (IDENT_ADDR + 0x87A0000040UL)
257 #define PYXIS_INT_HILO (IDENT_ADDR + 0x87A00000C0UL)
258 #define PYXIS_INT_ROUTE (IDENT_ADDR + 0x87A0000140UL)
259 #define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL)
260 #define PYXIS_INT_CNFG (IDENT_ADDR + 0x87A00001C0UL)
261 #define PYXIS_RT_COUNT (IDENT_ADDR + 0x87A0000200UL)
262 #define PYXIS_INT_TIME (IDENT_ADDR + 0x87A0000240UL)
263 #define PYXIS_IIC_CTRL (IDENT_ADDR + 0x87A00002C0UL)
264 #define PYXIS_RESET (IDENT_ADDR + 0x8780000900UL)
541 return addr >= IDENT_ADDR + 0x8000000000UL;