Searched refs:BIT2 (Results 1 - 22 of 22) sorted by relevance

/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/scsi/
H A Dtmscsim.h286 #define BIT2 0x00000004 macro
293 #define FORMATING_MEDIA BIT2
299 #define ASPI_SUPPORT BIT2
305 #define SRB_MSGOUT BIT2 /*;arbitration+msg_out 1st byte*/
322 #define OVER_RUN BIT2
330 #define RESET_DONE BIT2
340 #define RESET_DEV0 BIT2
384 #define WIDE_ENABLE BIT2 /* Not used ;-) */
490 #define EN_DISCONNECT_ BIT2
497 #define RST_SCSI_BUS BIT2
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/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-arm/arch-integrator/
H A Dbits.h28 #define BIT2 0x00000004 macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-arm/arch-integrator/
H A Dbits.h28 #define BIT2 0x00000004 macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/arch/mips/galileo-boards/ev64120/
H A Di2o.c281 return (regData & BIT2);
300 return (regData & BIT2);
312 SET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2);
325 RESET_REG_BITS(INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2);
338 SET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2);
351 RESET_REG_BITS(OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE, BIT2);
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm-mips/galileo-boards/evb64120A/
H A Ddma.h19 #define DECREMENT_SOURCE_ADDRESS BIT2
H A Dcore.h19 #define BIT2 0x00000004 macro
H A Dpci.h62 #define MASTER_ENABLE BIT2
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm-mips/galileo-boards/evb64120A/
H A Ddma.h19 #define DECREMENT_SOURCE_ADDRESS BIT2
H A Dcore.h19 #define BIT2 0x00000004 macro
H A Dpci.h62 #define MASTER_ENABLE BIT2
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/asm/galileo-boards/evb64120A/
H A Ddma.h19 #define DECREMENT_SOURCE_ADDRESS BIT2
H A Dcore.h19 #define BIT2 0x00000004 macro
H A Dpci.h62 #define MASTER_ENABLE BIT2
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/asm/galileo-boards/evb64120A/
H A Ddma.h19 #define DECREMENT_SOURCE_ADDRESS BIT2
H A Dcore.h19 #define BIT2 0x00000004 macro
H A Dpci.h62 #define MASTER_ENABLE BIT2
/asus-wl-520gu-7.0.1.45/src/router/iproute2/reference/linux/
H A Dsynclink.h22 #define BIT2 0x0004 macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/include/linux/
H A Dsynclink.h22 #define BIT2 0x0004 macro
/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/char/pcmcia/
H A Dsynclink_cs.c329 #define IRQ_DCD BIT2 // carrier detect status change
336 #define CEC BIT2 // command executing
341 #define PVR_RI BIT2
892 while ((status = read_reg(info, (unsigned char)(channel+STAR)) & BIT2)) {
1406 if (gis & (BIT3 + BIT2))
1453 if (pis & BIT2)
3416 val |= BIT2;
3488 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
3559 val |= BIT2;
3582 val |= BIT4 + BIT2;
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/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/char/
H A Dsynclink.c526 #define TRANSMIT_DATA BIT2
544 #define RXSTATUS_ABORT BIT2
545 #define RXSTATUS_PARITY_ERROR BIT2
583 #define TXSTATUS_ALL_SENT BIT2
603 #define MISCSTATUS_DPLL_NO_SYNC BIT2
629 #define SICR_DPLL_NO_SYNC BIT2
655 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
663 #define TXSTATUS_ALL_SENT BIT2
684 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
1615 * BIT2 EO
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H A Dsynclinkmp.c450 #define CDCD BIT2
466 #define CRCE BIT2
2536 if (status & BIT2 << shift)
2545 if (dmastatus & BIT2 << shift)
4409 case 7: RegValue |= BIT4 + BIT2; break;
4411 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4547 RegValue |= BIT2 + BIT1;
4746 if ( !(status & BIT2))
4904 status &= ~BIT2;
4918 if (status & (BIT6+BIT5+BIT3+BIT2)) {
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/asus-wl-520gu-7.0.1.45/src/linux/linux/drivers/acpi/include/
H A Dacmacros.h52 #define BIT2(x) ((((x) & 0x04) > 0) ? 1 : 0) macro

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