1/* PCI.h - PCI functions header file */
2
3/* Copyright - Galileo technology. */
4
5#ifndef  __INCpcih
6#define  __INCpcih
7
8/* includes */
9
10#include"core.h"
11
12/* defines */
13
14#define PCI0_MASTER_ENABLE(deviceNumber) pci0WriteConfigReg(                  \
15          PCI_0STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |                \
16          pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
17
18#define PCI0_MASTER_DISABLE(deviceNumber) pci0WriteConfigReg(                 \
19          PCI_0STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &               \
20          pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
21
22#define PCI1_MASTER_ENABLE(deviceNumber) pci1WriteConfigReg(                  \
23          PCI_0STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |                \
24          pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
25
26#define PCI1_MASTER_DISABLE(deviceNumber) pci1WriteConfigReg(                 \
27          PCI_0STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &               \
28          pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
29
30#define PCI0_MEMORY_ENABLE(deviceNumber) pci0WriteConfigReg(                  \
31          PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |                \
32          pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
33
34#define PCI1_MEMORY_ENABLE(deviceNumber) pci1WriteConfigReg(                  \
35          PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |                \
36          pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
37
38#define PCI0_IO_ENABLE(deviceNumber) pci0WriteConfigReg(                      \
39          PCI_0STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |                   \
40          pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
41
42#define PCI1_IO_ENABLE(deviceNumber) pci1WriteConfigReg(                      \
43          PCI_0STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |                   \
44          pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
45
46#define PCI0_SLAVE_ENABLE(deviceNumber) pci0WriteConfigReg(                   \
47          PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \
48          pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
49
50#define PCI1_SLAVE_ENABLE(deviceNumber) pci1WriteConfigReg(                   \
51          PCI_0STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \
52          pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber) )
53
54#define PCI0_DISABLE(deviceNumber) pci0WriteConfigReg(                        \
55          PCI_0STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &                  \
56          pci0ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber))
57
58#define PCI1_DISABLE(deviceNumber) pci1WriteConfigReg(                        \
59          PCI_0STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &                  \
60          pci1ReadConfigReg(PCI_0STATUS_AND_COMMAND,deviceNumber))
61
62#define 	MASTER_ENABLE			BIT2
63#define		MEMORY_ENABLE			BIT1
64#define		I_O_ENABLE  			BIT0
65#define     SELF                    0
66/* Agent on the PCI bus may have up to 6 BARS. */
67#define     BAR0                    0x10
68#define     BAR1                    0x14
69#define     BAR2                    0x18
70#define     BAR3                    0x1c
71#define     BAR4                    0x20
72#define     BAR5                    0x24
73
74
75/* typedefs */
76
77typedef struct pciDevice
78{
79    char            type[20];
80    unsigned int    deviceNum;
81    unsigned int    venID;
82    unsigned int    deviceID;
83    unsigned int    bar0Base;
84    unsigned int    bar0Size;
85    unsigned int    bar0Type;
86    unsigned int    bar1Base;
87    unsigned int    bar1Size;
88    unsigned int    bar1Type;
89    unsigned int    bar2Base;
90    unsigned int    bar2Size;
91    unsigned int    bar2Type;
92    unsigned int    bar3Base;
93    unsigned int    bar3Size;
94    unsigned int    bar3Type;
95    unsigned int    bar4Base;
96    unsigned int    bar4Size;
97    unsigned int    bar4Type;
98    unsigned int    bar5Base;
99    unsigned int    bar5Size;
100    unsigned int    bar5Type;
101} PCI_DEVICE;
102
103void    pci0WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,
104                           unsigned int data);
105void    pci1WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,
106                           unsigned int data);
107void    pci0ScanDevices(PCI_DEVICE *pci0Detect,unsigned int numberOfElment);
108void    pci1ScanDevices(PCI_DEVICE *pci1Detect,unsigned int numberOfElment);
109unsigned int    pci0ReadConfigReg (unsigned int regOffset,
110                                   unsigned int pciDevNum);
111unsigned int    pci1ReadConfigReg (unsigned int regOffset,
112                                   unsigned int pciDevNum);
113
114/*      Master`s memory space   */
115
116void    pci0MapIOspace(unsigned int pci0IoBase,unsigned int pci0IoLength);
117void    pci0MapMemory0space(unsigned int pci0Mem0Base,
118                            unsigned int pci0Mem0Length);
119void    pci0MapMemory1space(unsigned int pci0Mem1Base,
120                            unsigned int pci0Mem1Length);
121
122void    pci1MapIOspace(unsigned int pci1IoBase,unsigned int pci1IoLength);
123void    pci1MapMemory0space(unsigned int pci1Mem0Base,
124                            unsigned int pci1Mem0Length);
125void    pci1MapMemory1space(unsigned int pci1Mem1Base,
126                            unsigned int pci1Mem1Length);
127
128unsigned int    pci0GetIOspaceBase(void);
129unsigned int    pci0GetIOspaceSize(void);
130unsigned int    pci0GetMemory0Base(void);
131unsigned int    pci0GetMemory0Size(void);
132unsigned int    pci0GetMemory1Base(void);
133unsigned int    pci0GetMemory1Size(void);
134
135unsigned int    pci1GetIOspaceBase(void);
136unsigned int    pci1GetIOspaceSize(void);
137unsigned int    pci1GetMemory0Base(void);
138unsigned int    pci1GetMemory0Size(void);
139unsigned int    pci1GetMemory1Base(void);
140unsigned int    pci1GetMemory1Size(void);
141
142/*      Slave`s memory space   */
143void    pci0MapInternalRegSpace(unsigned int pci0InternalBase);
144void    pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
145void    pci0MapMemoryBanks0_1(unsigned int pci0Dram0_1Base,
146                              unsigned int pci0Dram0_1Size);
147void    pci0MapMemoryBanks2_3(unsigned int pci0Dram2_3Base,
148                              unsigned int pci0Dram2_3Size);
149void    pci0MapDevices0_1and2MemorySpace(unsigned int pci0Dev012Base,
150                                         unsigned int pci0Dev012Length);
151void    pci0MapDevices3andBootMemorySpace(unsigned int pci0Dev3andBootBase,
152                                          unsigned int pci0Dev3andBootLength);
153
154void    pci1MapInternalRegSpace(unsigned int pci1InternalBase);
155void    pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
156void    pci1MapMemoryBanks0_1(unsigned int pci1Dram0_1Base,
157                              unsigned int pci1Dram0_1Size);
158void    pci1MapMemoryBanks2_3(unsigned int pci1Dram2_3Base,
159                              unsigned int pci1Dram2_3Size);
160void    pci1MapDevices0_1and2MemorySpace(unsigned int pci1Dev012Base,
161                                         unsigned int pci1Dev012Length);
162void    pci1MapDevices3andBootMemorySpace(unsigned int pci1Dev3andBootBase,
163                                          unsigned int pci1Dev3andBootLength);
164
165#endif  /* __INCpcih */
166