/linux-master/arch/x86/crypto/ |
H A D | sha256_ssse3_glue.c | 33 #include <crypto/internal/simd.h> 42 #include <asm/simd.h>
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H A D | sm4_aesni_avx_glue.c | 14 #include <asm/simd.h> 15 #include <crypto/internal/simd.h>
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H A D | aegis128-aesni-glue.c | 11 #include <crypto/internal/simd.h>
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H A D | aria_aesni_avx2_glue.c | 9 #include <crypto/internal/simd.h>
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H A D | aria_aesni_avx_glue.c | 9 #include <crypto/internal/simd.h>
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H A D | aria_gfni_avx512_glue.c | 9 #include <crypto/internal/simd.h>
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H A D | aesni-intel_glue.c | 29 #include <asm/simd.h> 32 #include <crypto/internal/simd.h>
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | gfx_v9_4_3.c | 556 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) argument 560 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 566 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, argument 572 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 582 uint32_t xcc_id, uint32_t simd, uint32_t wave, 587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wav 581 gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 604 gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) argument 612 gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) argument [all...] |
H A D | amdgpu_debugfs.c | 434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); 439 adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread, *pos, size>>2, data); 442 adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, data); 1061 uint32_t offset, se, sh, cu, wave, simd, data[32]; local 1072 simd = (*pos & GENMASK_ULL(44, 37)) >> 37; 1092 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x); 1153 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; local 1164 simd = (*pos & GENMASK_ULL(51, 44)) >> 44; 1186 adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data); 1189 adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wav [all...] |
H A D | gfx_v7_0.c | 4087 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) argument 4091 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4097 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, argument 4103 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 4112 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 4116 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 4117 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 4118 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 4119 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 4120 dst[(*no_fields)++] = wave_read_ind(adev, simd, wav 4137 gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) argument [all...] |
H A D | gfx_v8_0.c | 5192 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) argument 5196 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 5202 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, argument 5208 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 5217 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 5221 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 5222 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 5223 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 5224 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 5225 dst[(*no_fields)++] = wave_read_ind(adev, simd, wav 5242 gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) argument [all...] |
H A D | gfx_v9_0.c | 1742 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) argument 1746 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1752 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, argument 1758 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1767 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 1771 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1772 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1773 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1774 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 1775 dst[(*no_fields)++] = wave_read_ind(adev, simd, wav 1788 gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst) argument 1797 gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst) argument [all...] |
H A D | gfx_v11_0.c | 807 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 812 WARN_ON(simd != 0); 833 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, argument 837 WARN_ON(simd != 0); 844 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, argument
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H A D | gfx_v10_0.c | 4280 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) argument 4286 WARN_ON(simd != 0); 4308 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, argument 4312 WARN_ON(simd != 0); 4319 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, argument
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/linux-master/crypto/ |
H A D | aegis128-core.c | 11 #include <crypto/internal/simd.h> 21 #include <asm/simd.h> 540 .base.cra_driver_name = "aegis128-simd", 581 MODULE_ALIAS_CRYPTO("aegis128-simd");
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H A D | Makefile | 211 crypto_simd-y := simd.o
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H A D | algapi.c | 9 #include <crypto/internal/simd.h>
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/linux-master/arch/arm64/crypto/ |
H A D | ghash-ce-glue.c | 9 #include <asm/simd.h> 18 #include <crypto/internal/simd.h>
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H A D | aes-neonbs-glue.c | 9 #include <asm/simd.h> 12 #include <crypto/internal/simd.h>
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H A D | sm4-ce-glue.c | 16 #include <asm/simd.h> 18 #include <crypto/internal/simd.h>
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H A D | aes-glue.c | 10 #include <asm/simd.h> 15 #include <crypto/internal/simd.h>
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/linux-master/arch/riscv/crypto/ |
H A D | aes-riscv64-glue.c | 15 #include <asm/simd.h> 19 #include <crypto/internal/simd.h>
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/linux-master/tools/testing/crypto/chacha20-s390/ |
H A D | test-cipher.c | 16 #include <crypto/internal/simd.h>
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/linux-master/arch/arm/crypto/ |
H A D | ghash-ce-glue.c | 11 #include <asm/simd.h> 19 #include <crypto/internal/simd.h>
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/linux-master/arch/arm64/kernel/ |
H A D | fpsimd.c | 42 #include <asm/simd.h>
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