Searched refs:sclk (Results 76 - 100 of 157) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dkv_dpm.h97 u32 sclk; member in struct:kv_pl
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddm_services_types.h63 struct dm_pp_clock_range sclk; member in struct:dm_pp_gpu_clock_range
/linux-master/drivers/gpu/drm/radeon/
H A Dradeon_pm.c174 u32 sclk, mclk; local
182 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 clock_info[rdev->pm.requested_clock_mode_index].sclk;
184 if (sclk > rdev->pm.default_sclk)
185 sclk = rdev->pm.default_sclk;
206 if (sclk < rdev->pm.current_sclk)
223 if (sclk != rdev->pm.current_sclk) {
225 radeon_set_engine_clock(rdev, sclk);
227 rdev->pm.current_sclk = sclk;
228 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
718 u32 sclk = 0; local
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H A Drv770_smc.h102 RV770_SMC_SCLK_VALUE sclk; member in struct:RV770_SMC_HW_PERFORMANCE_LEVEL
H A Dradeon_clocks.c43 uint32_t fb_div, ref_div, post_div, sclk; local
56 sclk = fb_div / ref_div;
60 sclk >>= 1;
62 sclk >>= 2;
64 sclk >>= 3;
66 return sclk;
H A Drv515.c919 fixed20_12 sclk; member in struct:rv515_watermark
931 fixed20_12 sclk; local
947 /* sclk in Mhz */
949 sclk.full = dfixed_const(selected_sclk);
950 sclk.full = dfixed_div(sclk, a);
1014 * sclk = system clock(Mhz)
1017 chunk_time.full = dfixed_div(a, sclk);
1102 fill_rate.full = dfixed_div(wm0->sclk, a);
1150 fill_rate.full = dfixed_div(wm0->sclk,
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H A Dradeon_i2c.c233 u32 sclk = rdev->pm.current_sclk; local
253 nm = (sclk * 10) / (i2c_clock * 4);
268 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
283 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
285 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
334 /* take the pm lock since we need a constant sclk */
587 /* take the pm lock since we need a constant sclk */
H A Dradeon_device.c721 * Used when sclk/mclk are switched or display modes are set.
727 u32 sclk = rdev->pm.current_sclk; local
730 /* sclk/mclk in Mhz */
732 rdev->pm.sclk.full = dfixed_const(sclk);
733 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
739 /* core_bandwidth = sclk(Mhz) * 16 */
740 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
H A Dnislands_smc.h102 NISLANDS_SMC_SCLK_VALUE sclk; member in struct:NISLANDS_SMC_HW_PERFORMANCE_LEVEL
/linux-master/drivers/spi/
H A Dspi-cadence-quadspi.c75 unsigned int sclk; member in struct:cqspi_st
1163 /* calculate the number of ref ticks for one sclk tick */
1164 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
1167 /* this particular value must be at least one sclk */
1193 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
1200 cqspi->sclk, ref_clk_hz/((div+1)*2));
1233 unsigned long sclk)
1237 int switch_ck = (cqspi->sclk != sclk);
1250 cqspi->sclk
1232 cqspi_configure(struct cqspi_flash_pdata *f_pdata, unsigned long sclk) argument
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.h89 uint16_t virtual_voltage_id, int32_t *sclk);
95 uint32_t sclk, uint16_t id, uint16_t *voltage);
H A Dsmu_helper.c462 uint16_t virtual_voltage_id, int32_t *sclk)
483 *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk;
583 uint32_t sclk, uint16_t id, uint16_t *voltage)
591 ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage);
595 ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol);
460 phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t virtual_voltage_id, int32_t *sclk) argument
582 phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t id, uint16_t *voltage) argument
H A Dsmu7_hwmgr.c1270 /* enable sclk deep sleep */
1352 /* disable sclk deep sleep */
2052 uint32_t sclk = 0; local
2068 table_info->vddgfx_lookup_table, vv_id, &sclk)) {
2074 if (sclk_table->entries[j].clk == sclk &&
2076 sclk += 5000;
2082 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
2100 table_info->vddc_lookup_table, vv_id, &sclk)) {
2108 if (sclk_table->entries[j].clk == sclk &&
2110 sclk
3321 uint32_t sclk; local
3999 uint32_t sclk, mclk, activity_percent; local
4085 uint32_t sclk = smu7_ps->performance_levels local
4135 uint32_t sclk, max_sclk = 0; local
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H A Dvega10_hwmgr.c528 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sclk */
557 uint32_t sclk = 0; local
568 table_info->vddc_lookup_table, vv_id, &sclk)) {
571 if (socclk_table->entries[j].clk == sclk &&
573 sclk += 5000;
580 VOLTAGE_TYPE_VDDC, sclk, vv_id, &vddc),
785 table_info->max_clock_voltage_on_ac.sclk =
794 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
795 table_info->max_clock_voltage_on_ac.sclk;
989 "Failed to init sclk threshol
3264 uint32_t sclk; local
3418 uint32_t sclk = vega10_ps->performance_levels local
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/linux-master/drivers/media/platform/rockchip/rga/
H A Drga.c707 ret = clk_prepare_enable(rga->sclk);
709 dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
730 clk_disable_unprepare(rga->sclk);
737 clk_disable_unprepare(rga->sclk);
776 rga->sclk = devm_clk_get(rga->dev, "sclk");
777 if (IS_ERR(rga->sclk)) {
778 dev_err(rga->dev, "failed to get sclk clock\n");
779 return PTR_ERR(rga->sclk);
/linux-master/drivers/video/fbdev/aty/
H A Dradeon_base.c562 rinfo->pll.sclk = (*val) / 10;
579 unsigned sclk, mclk, tmp, ref_div; local
694 sclk = round_div((2 * Ns * xtal), (2 * M));
700 rinfo->pll.sclk = sclk;
722 rinfo->pll.sclk = 23000;
733 rinfo->pll.sclk = 27500;
743 rinfo->pll.sclk = 25000;
753 rinfo->pll.sclk = 27000;
764 rinfo->pll.sclk
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/linux-master/drivers/gpu/drm/amd/display/dc/basics/
H A Ddce_calcs.c100 struct bw_fixed *sclk; local
127 sclk = kcalloc(8, sizeof(*sclk), GFP_KERNEL);
128 if (!sclk)
142 sclk[s_low] = vbios->low_sclk;
143 sclk[s_mid1] = vbios->mid1_sclk;
144 sclk[s_mid2] = vbios->mid2_sclk;
145 sclk[s_mid3] = vbios->mid3_sclk;
146 sclk[s_mid4] = vbios->mid4_sclk;
147 sclk[s_mid
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/linux-master/sound/soc/codecs/
H A Drt1308.c435 static int rt1308_get_clk_info(int sclk, int rate) argument
440 if (sclk <= 0 || rate <= 0)
445 if (sclk == rate * pd[i])
H A Dtas5086.c241 unsigned int mclk, sclk; member in struct:tas5086_private
307 priv->sclk = freq;
394 (priv->sclk == 48 * priv->rate) ?
H A Dcs35l35.h283 int sclk; member in struct:cs35l35_private
/linux-master/drivers/net/ethernet/marvell/octeontx2/af/
H A Dptp.c367 void ptp_start(struct rvu *rvu, u64 sclk, u32 ext_clk_freq, u32 extts) argument
379 if (!sclk) {
384 /* sclk is in MHz */
385 ptp->clock_rate = sclk * 1000000;
/linux-master/arch/mips/txx9/generic/
H A Dsetup.c372 unsigned int line, unsigned int sclk, int nocts)
385 if (sclk) {
387 req.uartclk = sclk;
371 txx9_sio_init(unsigned long baseaddr, int irq, unsigned int line, unsigned int sclk, int nocts) argument
H A Dsetup_tx4938.c288 void __init tx4938_sio_init(unsigned int sclk, unsigned int cts_mask) argument
300 i, sclk, (1 << i) & cts_mask);
/linux-master/sound/soc/bcm/
H A Dcygnus-ssp.c538 u32 sclk; local
573 /* Set sclk rate */
576 sclk = aio->bit_per_frame;
577 if (sclk == 512)
578 sclk = 0;
580 /* sclks_per_1fs_div = sclk cycles/32 */
581 sclk /= 32;
586 value |= sclk << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32;
/linux-master/arch/mips/include/asm/txx9/
H A Dtx4927.h264 void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);

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