Searched refs:reg (Results 76 - 100 of 7209) sorted by relevance

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/linux-master/drivers/clk/
H A Dclk-highbank.c39 void __iomem *reg; member in struct:hb_clk
47 u32 reg; local
49 reg = readl(hbclk->reg);
50 reg &= ~HB_PLL_RESET;
51 writel(reg, hbclk->reg);
53 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
55 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
64 u32 reg; local
74 u32 reg; local
86 u32 reg; local
97 unsigned long divf, divq, vco_freq, reg; local
150 u32 reg; local
265 u32 reg; local
[all...]
/linux-master/drivers/scsi/qla2xxx/
H A Dqla_dbg.c107 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local
118 if (qla_pci_disconnected(vha, reg))
125 wrt_reg_word(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
126 wrt_reg_word(&reg->mailbox1, LSW(addr));
127 wrt_reg_word(&reg->mailbox8, MSW(addr));
129 wrt_reg_word(&reg->mailbox2, MSW(LSD(dump_dma)));
130 wrt_reg_word(&reg->mailbox3, LSW(LSD(dump_dma)));
131 wrt_reg_word(&reg->mailbox6, MSW(MSD(dump_dma)));
132 wrt_reg_word(&reg->mailbox7, LSW(MSD(dump_dma)));
134 wrt_reg_word(&reg
195 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local
296 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, uint32_t count, __be32 *buf) argument
310 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha) argument
326 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local
383 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; local
462 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, __be16 *buf) argument
677 device_reg_t *reg; local
745 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; local
902 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; local
1083 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local
1329 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local
1642 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local
1957 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; local
2667 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; local
[all...]
/linux-master/drivers/gpu/drm/xe/
H A Dxe_mmio.h27 static inline u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg) argument
31 if (reg.addr < gt->mmio.adj_limit)
32 reg.addr += gt->mmio.adj_offset;
34 return readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr);
37 static inline u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg) argument
41 if (reg.addr < gt->mmio.adj_limit)
42 reg.addr += gt->mmio.adj_offset;
44 return readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg
47 xe_mmio_write32(struct xe_gt *gt, struct xe_reg reg, u32 val) argument
58 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg) argument
68 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set) argument
80 xe_mmio_write32_and_verify(struct xe_gt *gt, struct xe_reg reg, u32 val, u32 mask, u32 eval) argument
92 xe_mmio_in_range(const struct xe_gt *gt, const struct xe_mmio_range *range, struct xe_reg reg) argument
[all...]
/linux-master/arch/powerpc/boot/dts/fsl/
H A Dpq3-esdhc-0.dtsi37 reg = <0x2e000 0x1000>;
H A Dpq3-mpic-message-B.dtsi37 reg = <0x42400 0x200>;
H A Dpq3-sata2-0.dtsi37 reg = <0x18000 0x1000>;
H A Dpq3-sata2-1.dtsi37 reg = <0x19000 0x1000>;
H A Dqoriq-esdhc-0.dtsi37 reg = <0x114000 0x1000>;
H A Dqoriq-sec4.0-0.dtsi40 reg = <0x300000 0x10000>;
46 reg = <0x1000 0x1000>;
52 reg = <0x2000 0x1000>;
58 reg = <0x3000 0x1000>;
64 reg = <0x4000 0x1000>;
72 reg = <0x6000 0x100>;
77 reg = <0x00 0x20 0x100 0x80>;
82 reg = <0x20 0x20 0x200 0x80>;
87 reg = <0x40 0x20 0x300 0x80>;
92 reg
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H A Dqoriq-sec4.2-0.dtsi40 reg = <0x300000 0x10000>;
47 reg = <0x1000 0x1000>;
54 reg = <0x2000 0x1000>;
61 reg = <0x3000 0x1000>;
68 reg = <0x4000 0x1000>;
77 reg = <0x6000 0x100>;
83 reg = <0x00 0x20 0x100 0x80>;
89 reg = <0x20 0x20 0x200 0x80>;
95 reg = <0x40 0x20 0x300 0x80>;
101 reg
[all...]
H A Dqoriq-sec5.0-0.dtsi40 reg = <0x300000 0x10000>;
47 reg = <0x1000 0x1000>;
54 reg = <0x2000 0x1000>;
61 reg = <0x3000 0x1000>;
68 reg = <0x4000 0x1000>;
77 reg = <0x6000 0x100>;
83 reg = <0x00 0x20 0x100 0x80>;
89 reg = <0x20 0x20 0x200 0x80>;
95 reg = <0x40 0x20 0x300 0x80>;
101 reg
[all...]
H A Dqoriq-sec5.2-0.dtsi40 reg = <0x300000 0x10000>;
48 reg = <0x1000 0x1000>;
56 reg = <0x2000 0x1000>;
64 reg = <0x3000 0x1000>;
72 reg = <0x4000 0x1000>;
82 reg = <0x6000 0x100>;
89 reg = <0x00 0x20 0x100 0x80>;
96 reg = <0x20 0x20 0x200 0x80>;
103 reg = <0x40 0x20 0x300 0x80>;
110 reg
[all...]
H A Dqoriq-sec5.3-0.dtsi40 reg = <0x300000 0x10000>;
48 reg = <0x1000 0x1000>;
56 reg = <0x2000 0x1000>;
64 reg = <0x3000 0x1000>;
72 reg = <0x4000 0x1000>;
82 reg = <0x6000 0x100>;
89 reg = <0x00 0x20 0x100 0x80>;
96 reg = <0x20 0x20 0x200 0x80>;
103 reg = <0x40 0x20 0x300 0x80>;
110 reg
[all...]
H A Dinterlaken-lac.dtsi37 reg = <0x229000 0x1000>;
43 reg = <0x228000 0x1000>;
/linux-master/tools/perf/arch/powerpc/include/
H A Ddwarf-regs-table.h10 #define REG_DWARFNUM_NAME(reg, idx) [idx] = "%" #reg
/linux-master/drivers/media/pci/cx23885/
H A Dcx23885-video.h10 int cx23885_flatiron_write(struct cx23885_dev *dev, u8 reg, u8 data);
11 u8 cx23885_flatiron_read(struct cx23885_dev *dev, u8 reg);
/linux-master/arch/arm/mach-omap2/
H A Dscrm44xx.h21 #define OMAP44XX_SCRM_REGADDR(reg) \
22 OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg))
/linux-master/arch/x86/include/asm/
H A Dxor_avx.h38 #define BLOCK(i, reg) \
40 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p1[i / sizeof(*p1)])); \
41 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
43 asm volatile("vmovdqa %%ymm" #reg ", %0" : \
66 #define BLOCK(i, reg) \
68 asm volatile("vmovdqa %0, %%ymm" #reg : : "m" (p2[i / sizeof(*p2)])); \
69 asm volatile("vxorps %0, %%ymm" #reg ", %%ymm" #reg : : \
71 asm volatile("vxorps %0, %%ymm" #reg ",
[all...]
H A Dmc146818rtc.h41 static inline void lock_cmos(unsigned char reg) argument
44 new = ((smp_processor_id() + 1) << 8) | reg;
70 #define lock_cmos_prefix(reg) \
74 lock_cmos(reg)
76 #define lock_cmos_suffix(reg) \
81 #define lock_cmos_prefix(reg) do {} while (0)
82 #define lock_cmos_suffix(reg) do {} while (0)
83 #define lock_cmos(reg) do { } while (0)
/linux-master/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn314.c43 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name)
48 #define DMUB_SR(reg) REG_OFFSET_EXP(reg),
55 #define DMUB_SF(reg, field) FD_MASK(reg, field),
59 #define DMUB_SF(reg, field) FD_SHIFT(reg, field),
/linux-master/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
H A Disys_dma_public.h25 const unsigned int reg,
30 const unsigned int reg);
/linux-master/drivers/acpi/pmic/
H A Dintel_pmic_bxtwc.c30 .reg = 0x63,
35 .reg = 0x65,
40 .reg = 0x67,
45 .reg = 0x6d,
50 .reg = 0x6f,
55 .reg = 0x70,
60 .reg = 0x71,
65 .reg = 0x72,
70 .reg = 0x73,
75 .reg
273 intel_bxtwc_pmic_get_power(struct regmap *regmap, int reg, int bit, u64 *value) argument
285 intel_bxtwc_pmic_update_power(struct regmap *regmap, int reg, int bit, bool on) argument
298 intel_bxtwc_pmic_get_raw_temp(struct regmap *regmap, int reg) argument
324 intel_bxtwc_pmic_update_aux(struct regmap *regmap, int reg, int raw) argument
351 intel_bxtwc_pmic_get_policy(struct regmap *regmap, int reg, int bit, u64 *value) argument
364 intel_bxtwc_pmic_update_policy(struct regmap *regmap, int reg, int bit, int enable) argument
[all...]
/linux-master/arch/mips/pci/
H A Dops-sni.c24 static int set_config_address(unsigned int busno, unsigned int devfn, int reg) argument
26 if ((devfn > 255) || (reg > 255))
35 (reg & 0xfc);
40 static int pcimt_read(struct pci_bus *bus, unsigned int devfn, int reg, argument
45 if ((res = set_config_address(bus->number, devfn, reg)))
50 *val = inb(PCIMT_CONFIG_DATA + (reg & 3));
53 *val = inw(PCIMT_CONFIG_DATA + (reg & 2));
63 static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg, argument
68 if ((res = set_config_address(bus->number, devfn, reg)))
73 outb(val, PCIMT_CONFIG_DATA + (reg
91 pcit_set_config_address(unsigned int busno, unsigned int devfn, int reg) argument
100 pcit_read(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 * val) argument
137 pcit_write(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 val) argument
[all...]
/linux-master/drivers/clk/sunxi-ng/
H A Dccu_frac.c19 return !(readl(common->base + common->reg) & cf->enable);
27 u32 reg; local
33 reg = readl(common->base + common->reg);
34 writel(reg & ~cf->enable, common->base + common->reg);
43 u32 reg; local
49 reg = readl(common->base + common->reg);
50 writel(reg | c
69 u32 reg; local
93 u32 reg, sel; local
[all...]
/linux-master/drivers/staging/media/starfive/camss/
H A Dstf-camss.h71 static inline u32 stf_isp_reg_read(struct stfcamss *stfcamss, u32 reg) argument
73 return ioread32(stfcamss->isp_base + reg);
77 u32 reg, u32 val)
79 iowrite32(val, stfcamss->isp_base + reg);
83 u32 reg, u32 val, u32 delay)
85 iowrite32(val, stfcamss->isp_base + reg);
90 u32 reg, u32 mask, u32 val)
94 value = ioread32(stfcamss->isp_base + reg) & ~mask;
97 iowrite32(val, stfcamss->isp_base + reg);
100 static inline void stf_isp_reg_set(struct stfcamss *stfcamss, u32 reg, u3 argument
76 stf_isp_reg_write(struct stfcamss *stfcamss, u32 reg, u32 val) argument
82 stf_isp_reg_write_delay(struct stfcamss *stfcamss, u32 reg, u32 val, u32 delay) argument
89 stf_isp_reg_set_bit(struct stfcamss *stfcamss, u32 reg, u32 mask, u32 val) argument
106 stf_syscon_reg_read(struct stfcamss *stfcamss, u32 reg) argument
111 stf_syscon_reg_write(struct stfcamss *stfcamss, u32 reg, u32 val) argument
117 stf_syscon_reg_set_bit(struct stfcamss *stfcamss, u32 reg, u32 bit_mask) argument
126 stf_syscon_reg_clear_bit(struct stfcamss *stfcamss, u32 reg, u32 bit_mask) argument
[all...]

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