1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * stf_camss.h
4 *
5 * Starfive Camera Subsystem driver
6 *
7 * Copyright (C) 2021-2023 StarFive Technology Co., Ltd.
8 */
9
10#ifndef STF_CAMSS_H
11#define STF_CAMSS_H
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/reset.h>
16#include <media/media-device.h>
17#include <media/media-entity.h>
18#include <media/v4l2-async.h>
19#include <media/v4l2-device.h>
20
21#include "stf-isp.h"
22#include "stf-capture.h"
23
24enum stf_port_num {
25	STF_PORT_DVP = 0,
26	STF_PORT_CSI2RX
27};
28
29enum stf_clk {
30	STF_CLK_WRAPPER_CLK_C = 0,
31	STF_CLK_ISPCORE_2X,
32	STF_CLK_ISP_AXI,
33	STF_CLK_NUM
34};
35
36enum stf_rst {
37	STF_RST_WRAPPER_P = 0,
38	STF_RST_WRAPPER_C,
39	STF_RST_AXIWR,
40	STF_RST_ISP_TOP_N,
41	STF_RST_ISP_TOP_AXI,
42	STF_RST_NUM
43};
44
45struct stf_isr_data {
46	const char *name;
47	irqreturn_t (*isr)(int irq, void *priv);
48};
49
50struct stfcamss {
51	struct v4l2_device v4l2_dev;
52	struct media_device media_dev;
53	struct media_pipeline pipe;
54	struct device *dev;
55	struct stf_isp_dev isp_dev;
56	struct stf_capture captures[STF_CAPTURE_NUM];
57	struct v4l2_async_notifier notifier;
58	void __iomem *syscon_base;
59	void __iomem *isp_base;
60	struct clk_bulk_data sys_clk[STF_CLK_NUM];
61	int nclks;
62	struct reset_control_bulk_data sys_rst[STF_RST_NUM];
63	int nrsts;
64};
65
66struct stfcamss_async_subdev {
67	struct v4l2_async_connection asd;  /* must be first */
68	enum stf_port_num port;
69};
70
71static inline u32 stf_isp_reg_read(struct stfcamss *stfcamss, u32 reg)
72{
73	return ioread32(stfcamss->isp_base + reg);
74}
75
76static inline void stf_isp_reg_write(struct stfcamss *stfcamss,
77				     u32 reg, u32 val)
78{
79	iowrite32(val, stfcamss->isp_base + reg);
80}
81
82static inline void stf_isp_reg_write_delay(struct stfcamss *stfcamss,
83					   u32 reg, u32 val, u32 delay)
84{
85	iowrite32(val, stfcamss->isp_base + reg);
86	usleep_range(1000 * delay, 1000 * delay + 100);
87}
88
89static inline void stf_isp_reg_set_bit(struct stfcamss *stfcamss,
90				       u32 reg, u32 mask, u32 val)
91{
92	u32 value;
93
94	value = ioread32(stfcamss->isp_base + reg) & ~mask;
95	val &= mask;
96	val |= value;
97	iowrite32(val, stfcamss->isp_base + reg);
98}
99
100static inline void stf_isp_reg_set(struct stfcamss *stfcamss, u32 reg, u32 mask)
101{
102	iowrite32(ioread32(stfcamss->isp_base + reg) | mask,
103		  stfcamss->isp_base + reg);
104}
105
106static inline u32 stf_syscon_reg_read(struct stfcamss *stfcamss, u32 reg)
107{
108	return ioread32(stfcamss->syscon_base + reg);
109}
110
111static inline void stf_syscon_reg_write(struct stfcamss *stfcamss,
112					u32 reg, u32 val)
113{
114	iowrite32(val, stfcamss->syscon_base + reg);
115}
116
117static inline void stf_syscon_reg_set_bit(struct stfcamss *stfcamss,
118					  u32 reg, u32 bit_mask)
119{
120	u32 value;
121
122	value = ioread32(stfcamss->syscon_base + reg);
123	iowrite32(value | bit_mask, stfcamss->syscon_base + reg);
124}
125
126static inline void stf_syscon_reg_clear_bit(struct stfcamss *stfcamss,
127					    u32 reg, u32 bit_mask)
128{
129	u32 value;
130
131	value = ioread32(stfcamss->syscon_base + reg);
132	iowrite32(value & ~bit_mask, stfcamss->syscon_base + reg);
133}
134#endif /* STF_CAMSS_H */
135