Searched refs:pasid (Results 76 - 100 of 120) sorted by relevance

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/linux-master/drivers/iommu/intel/
H A Diommu.c30 #include "pasid.h"
762 unsigned long long addr, u32 pasid)
805 /* get the pointer to pasid directory entry */
808 pr_info("pasid directory entry is not present\n");
811 /* For request-without-pasid, get the pasid from context entry */
812 if (intel_iommu_sm && pasid == IOMMU_PASID_INVALID)
813 pasid = IOMMU_NO_PASID;
815 dir_index = pasid >> PASID_PDE_SHIFT;
817 pr_info("pasid di
761 dmar_fault_dump_ptes(struct intel_iommu *iommu, u16 source_id, unsigned long long addr, u32 pasid) argument
2205 domain_setup_first_level(struct intel_iommu *iommu, struct dmar_domain *domain, struct device *dev, u32 pasid) argument
4593 intel_iommu_remove_dev_pasid(struct device *dev, ioasid_t pasid) argument
4636 intel_iommu_set_dev_pasid(struct iommu_domain *domain, struct device *dev, ioasid_t pasid) argument
5087 quirk_extra_dev_tlb_flush(struct device_domain_info *info, unsigned long address, unsigned long mask, u32 pasid, u16 qdep) argument
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H A Dcap_audit.c60 CHECK_FEATURE_MISMATCH(a, b, ecap, pasid, ECAP_PASID_MASK);
106 CHECK_FEATURE_MISMATCH_HOTPLUG(iommu, ecap, pasid, ECAP_PASID_MASK);
H A Ddmar.c1576 void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr, argument
1592 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1604 desc.qw0 = QI_EIOTLB_PASID(pasid) |
1618 u32 pasid, u16 qdep, u64 addr, unsigned int size_order)
1632 desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
1670 u64 granu, u32 pasid)
1674 desc.qw0 = QI_PC_PASID(pasid) | QI_PC_DID(did) |
1986 u8 fault_reason, u32 pasid, u16 source_id,
2003 if (pasid == IOMMU_PASID_INVALID)
2011 type ? "DMA Read" : "DMA Write", pasid,
1617 qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid, u32 pasid, u16 qdep, u64 addr, unsigned int size_order) argument
1669 qi_flush_pasid_cache(struct intel_iommu *iommu, u16 did, u64 granu, u32 pasid) argument
1985 dmar_fault_do_one(struct intel_iommu *iommu, int type, u8 fault_reason, u32 pasid, u16 source_id, unsigned long long addr) argument
2049 u32 pasid; local
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/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_smi_events.c239 void kfd_smi_event_update_vmfault(struct kfd_node *dev, uint16_t pasid) argument
243 task_info = amdgpu_vm_get_task_info_pasid(dev->adev, pasid);
H A Dkfd_debug.c198 unsigned int pasid,
207 p = kfd_lookup_process_by_pasid(pasid);
239 kfd_dqm_evict_pasid(dev->dqm, p->pasid);
240 kfd_signal_vm_fault_event(dev, p->pasid, NULL,
277 kfd_dqm_evict_pasid(pdd->dev->dqm, p->pasid);
278 kfd_signal_vm_fault_event(pdd->dev, p->pasid, NULL, data);
197 kfd_set_dbg_ev_from_interrupt(struct kfd_node *dev, unsigned int pasid, uint32_t doorbell_id, uint64_t trap_mask, void *exception_data, size_t exception_data_size) argument
H A Dkfd_device_queue_manager.c46 u32 pasid, unsigned int vmid);
201 queue_input.process_id = qpd->pqm->process->pasid;
468 dqm->vmid_pasid[allocated_vmid] = q->process->pasid;
470 set_pasid_vmid_mapping(dqm, q->process->pasid, allocated_vmid);
486 /* invalidate the VM context after pasid and vmid mapping is set up */
718 dev_err(dev->adev->dev, "no vmid pasid mapping supported\n");
731 if (status && queried_pasid == p->pasid) {
732 pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
733 vmid, p->pasid);
739 dev_err(dev->adev->dev, "Didn't find vmid for pasid
1371 set_pasid_vmid_mapping(struct device_queue_manager *dqm, u32 pasid, unsigned int vmid) argument
2022 reset_queues_cpsch(struct device_queue_manager *dqm, uint16_t pasid) argument
2649 kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid) argument
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H A Dkfd_device_queue_manager.h187 uint16_t pasid);
245 /* the pasid mapping for each kfd vmid */
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v7_0.c416 * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
419 * @pasid: pasid to be flush
424 * Flush the TLB for the requested pasid.
427 uint16_t pasid, uint32_t flush_type,
437 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid)
487 unsigned int pasid)
489 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
755 * @pasid: debug logging only - no functional use
760 u32 addr, u32 mc_client, unsigned int pasid)
426 gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, uint32_t flush_type, bool all_hub, uint32_t inst) argument
486 gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, unsigned int pasid) argument
759 gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, u32 addr, u32 mc_client, unsigned int pasid) argument
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H A Dgmc_v9_0.c597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
630 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name,
632 entry->src_id, entry->ring_id, entry->vmid, entry->pasid);
634 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
669 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub);
927 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
930 * @pasid: pasid t
937 gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, uint32_t flush_type, bool all_hub, uint32_t inst) argument
1014 gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, unsigned int pasid) argument
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H A Dgmc_v8_0.c606 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
609 * @pasid: pasid to be flush
614 * Flush the TLB for the requested pasid.
617 uint16_t pasid, uint32_t flush_type,
627 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid)
677 unsigned int pasid)
679 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
986 * @pasid: debug logging only - no functional use
991 u32 addr, u32 mc_client, unsigned int pasid)
616 gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, uint32_t flush_type, bool all_hub, uint32_t inst) argument
676 gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, unsigned int pasid) argument
990 gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, u32 addr, u32 mc_client, unsigned int pasid) argument
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H A Damdgpu_amdkfd_gfx_v9.c101 int kgd_gfx_v9_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid, argument
111 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
133 /* Mapping vmid to pasid also for IH block */
150 /* Mapping vmid to pasid also for IH block */
980 * process whose pasid is provided as a parameter. The process could have ZERO
984 * @pasid: Identifies the process for which this query call is invoked
986 * belong to process with given pasid
1017 * Determine if VMID from above step maps to pasid provided as parameter. If
1018 * it matches agrregate the wave count. That the VMID will not match pasid i
1024 kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, int *pasid_wave_cnt, int *max_waves_per_cu, uint32_t inst) argument
[all...]
H A Damdgpu_umsch_mm.c74 uint32_t pasid; member in struct:umsch_mm_test
215 queue_input.process_id = test->pasid;
335 test->pasid = r;
385 amdgpu_pasid_free(test->pasid);
405 amdgpu_pasid_free(test->pasid);
H A Damdgpu_amdkfd_gfx_v10_3.c96 static int set_pasid_vmid_mapping_v10_3(struct amdgpu_device *adev, unsigned int pasid, argument
99 uint32_t value = pasid << IH_VMID_0_LUT__PASID__SHIFT;
101 /* Mapping vmid to pasid also for IH block */
102 pr_debug("mapping vmid %d -> pasid %d in IH block for GFX client\n",
103 vmid, pasid);
H A Damdgpu_amdkfd_gfx_v8.c87 static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid, argument
97 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
106 /* Mapping vmid to pasid also for IH block */
H A Damdgpu_ih.c276 entry->pasid = dw[3] & 0xffff;
H A Damdgpu_amdkfd_gfx_v10.c95 static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid, argument
105 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
108 pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping);
128 /* Mapping vmid to pasid also for IH block */
H A Dcik_ih.c266 entry->pasid = (dw[2] >> 16) & 0xffff;
H A Dtonga_ih.c260 entry->pasid = (dw[2] >> 16) & 0xffff;
H A Diceland_ih.c256 entry->pasid = (dw[2] >> 16) & 0xffff;
H A Dcz_ih.c257 entry->pasid = (dw[2] >> 16) & 0xffff;
H A Damdgpu_job.c65 ti = amdgpu_vm_get_task_info_pasid(ring->adev, job->pasid);
/linux-master/drivers/gpu/drm/msm/adreno/
H A Dadreno_gpu.c31 u32 pasid)
141 ret = qcom_mdt_load(dev, fw, fwname, pasid,
148 ret = qcom_mdt_load(dev, fw, newname, pasid,
156 ret = qcom_scm_pas_auth_and_reset(pasid);
176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) argument
191 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid);
30 zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, u32 pasid) argument
/linux-master/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3-sva.c359 static int __arm_smmu_sva_bind(struct device *dev, ioasid_t pasid, argument
389 ret = arm_smmu_write_ctx_desc(master, pasid, bond->smmu_mn->cd);
/linux-master/drivers/misc/ocxl/
H A Dconfig.c710 dev_dbg(&dev->dev, " pasid supported (log) = %u\n",
887 int ocxl_config_terminate_pasid(struct pci_dev *dev, int afu_control, int pasid) argument
897 pasid);
902 val |= pasid & OCXL_DVSEC_PASID_MASK;
915 pasid);
/linux-master/arch/x86/include/asm/fpu/
H A Dtypes.h311 u64 pasid; member in struct:ia32_pasid_state

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