Searched refs:mmio (Results 76 - 100 of 429) sorted by relevance

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/linux-master/arch/arm64/kvm/
H A Dmmio.c97 data = kvm_mmio_read_buf(run->mmio.data, len);
108 trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr,
179 run->mmio.is_write = is_write;
180 run->mmio.phys_addr = fault_ipa;
181 run->mmio.len = len;
187 memcpy(run->mmio.data, data_buf, len);
194 memcpy(run->mmio.data, data_buf, len);
H A DMakefile13 kvm-y += arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \
21 vgic/vgic-mmio.o vgic/vgic-mmio-v2.o \
22 vgic/vgic-mmio-v3.o vgic/vgic-kvm-device.o \
/linux-master/drivers/gpu/drm/msm/adreno/
H A Da6xx_gmu.h55 void __iomem *mmio; member in struct:a6xx_gmu
106 return msm_readl(gmu->mmio + (offset << 2));
111 msm_writel(value, gmu->mmio + (offset << 2));
117 memcpy_toio(gmu->mmio + (offset << 2), data, size);
134 val = (u64) msm_readl(gmu->mmio + (lo << 2));
135 val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
141 readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
/linux-master/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_rapl.c26 /* mmio rapl supports package 0 only for now */
60 if (!ra->reg.mmio)
63 ra->value = readq(ra->reg.mmio);
72 if (!ra->reg.mmio)
75 val = readq(ra->reg.mmio);
78 writeq(val, ra->reg.mmio);
95 rapl_mmio_priv.regs[domain][reg].mmio =
101 rapl_mmio_priv.reg_unit.mmio = proc_priv->mmio_base + rapl_regs->reg_unit;
106 rapl_mmio_priv.control_type = powercap_register_control_type(NULL, "intel-rapl-mmio", NULL);
/linux-master/drivers/bcma/
H A Dhost_pci.c45 return ioread8(core->bus->mmio + offset);
51 return ioread16(core->bus->mmio + offset);
57 return ioread32(core->bus->mmio + offset);
64 iowrite8(value, core->bus->mmio + offset);
71 iowrite16(value, core->bus->mmio + offset);
78 iowrite32(value, core->bus->mmio + offset);
85 void __iomem *addr = core->bus->mmio + offset;
109 void __iomem *addr = core->bus->mmio + offset;
134 return ioread32(core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
142 iowrite32(value, core->bus->mmio
[all...]
/linux-master/drivers/ata/
H A Dsata_nv.c599 void __iomem *mmio = pp->ctl_block; local
606 status = readw(mmio + NV_ADMA_STAT);
609 status = readw(mmio + NV_ADMA_STAT);
616 tmp = readw(mmio + NV_ADMA_CTL);
617 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
620 status = readw(mmio + NV_ADMA_STAT);
623 status = readw(mmio + NV_ADMA_STAT);
637 void __iomem *mmio = pp->ctl_block; local
646 tmp = readw(mmio + NV_ADMA_CTL);
647 writew(tmp | NV_ADMA_CTL_GO, mmio
887 void __iomem *mmio = pp->ctl_block; local
1015 void __iomem *mmio = pp->ctl_block; local
1037 void __iomem *mmio = pp->ctl_block; local
1055 void __iomem *mmio = pp->ctl_block; local
1100 void __iomem *mmio; local
1190 void __iomem *mmio = pp->ctl_block; local
1199 void __iomem *mmio = pp->ctl_block; local
1216 void __iomem *mmio = pp->ctl_block; local
1250 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; local
1394 void __iomem *mmio = pp->ctl_block; local
1629 void __iomem *mmio = pp->ctl_block; local
1809 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; local
1828 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; local
1848 void __iomem *mmio = host->iomap[NV_MMIO_BAR]; local
1920 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR]; local
[all...]
/linux-master/drivers/hid/amd-sfh-hid/
H A Damd_sfh_pcie.c46 if (!readl_poll_timeout(mp2->mmio + AMD_P2C_MSG(0), cmd_resp.resp,
69 writeq(info.dma_address, privdata->mmio + AMD_C2P_MSG1);
70 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
84 writeq(0x0, privdata->mmio + AMD_C2P_MSG1);
85 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
97 writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
102 if (readl(privdata->mmio + amd_get_p2c_val(privdata, 4))) {
103 writel(0, privdata->mmio + amd_get_p2c_val(privdata, 4));
104 writel(0xf, privdata->mmio + amd_get_p2c_val(privdata, 5));
140 return (readl(privdata->mmio
[all...]
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dmmio.c248 void *mmio = gvt->firmware.mmio; local
251 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
296 * interrupt include DE,display mmio related will not be
299 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
315 vgpu->mmio.vreg = vzalloc(info->mmio_size);
316 if (!vgpu->mmio.vreg)
331 vfree(vgpu->mmio
[all...]
/linux-master/drivers/comedi/drivers/
H A Dii_pci20kc.c140 return dev->mmio + (s->index + 1) * II20K_MOD_OFFSET;
312 writeb(ctrl01, dev->mmio + II20K_CTRL01_REG);
313 writeb(ctrl23, dev->mmio + II20K_CTRL23_REG);
314 writeb(dir_ena, dev->mmio + II20K_DIR_ENA_REG);
355 dev->mmio + II20K_DIO0_REG);
358 dev->mmio + II20K_DIO1_REG);
361 dev->mmio + II20K_DIO2_REG);
364 dev->mmio + II20K_DIO3_REG);
367 data[1] = readb(dev->mmio + II20K_DIO0_REG);
368 data[1] |= readb(dev->mmio
[all...]
H A Dni_670x.c94 dev->mmio + AO_CHAN_OFFSET);
96 writel(val, dev->mmio + AO_VALUE_OFFSET);
109 writel(s->state, dev->mmio + DIO_PORT0_DATA_OFFSET);
111 data[1] = readl(dev->mmio + DIO_PORT0_DATA_OFFSET);
127 writel(s->io_bits, dev->mmio + DIO_PORT0_DIR_OFFSET);
184 dev->mmio = pci_ioremap_bar(pcidev, 1);
185 if (!dev->mmio)
231 writel(0x10, dev->mmio + MISC_CONTROL_OFFSET);
233 writel(0x00, dev->mmio + AO_CONTROL_OFFSET);
H A Dmf6x4.c88 data[1] = ioread16(dev->mmio + MF6X4_DIN_REG) & MF6X4_DIN_MASK;
99 iowrite16(s->state, dev->mmio + MF6X4_DOUT_REG);
132 iowrite16(MF6X4_ADCTRL_CHAN(chan), dev->mmio + MF6X4_ADCTRL_REG);
136 ioread16(dev->mmio + MF6X4_ADSTART_REG);
143 d = ioread16(dev->mmio + MF6X4_ADDATA_REG);
149 iowrite16(0x0, dev->mmio + MF6X4_ADCTRL_REG);
172 iowrite16(val, dev->mmio + MF6X4_DAC_REG(chan));
207 dev->mmio = pci_ioremap_bar(pcidev, board->bar_nums[1]);
208 if (!dev->mmio)
/linux-master/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c137 void __iomem *mmio; member in struct:rockchip_combphy_priv
156 temp = readl(priv->mmio + reg);
158 writel(temp, priv->mmio + reg);
338 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
339 if (IS_ERR(priv->mmio)) {
340 ret = PTR_ERR(priv->mmio);
407 val = readl(priv->mmio + PHYREG15);
409 writel(val, priv->mmio + PHYREG15);
417 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
424 writel(PHYREG18_PLL_LOOP, priv->mmio
[all...]
/linux-master/drivers/ntb/hw/intel/
H A Dntb_hw_gen1.c203 void __iomem *mmio)
208 return ndev->reg->db_ioread(mmio);
212 void __iomem *mmio)
220 ndev->reg->db_iowrite(db_bits, mmio);
226 void __iomem *mmio)
239 ndev->reg->db_iowrite(ndev->db_mask, mmio);
247 void __iomem *mmio)
260 ndev->reg->db_iowrite(ndev->db_mask, mmio);
297 void __iomem *mmio)
305 return ioread32(mmio
202 ndev_db_read(struct intel_ntb_dev *ndev, void __iomem *mmio) argument
211 ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits, void __iomem *mmio) argument
225 ndev_db_set_mask(struct intel_ntb_dev *ndev, u64 db_bits, void __iomem *mmio) argument
246 ndev_db_clear_mask(struct intel_ntb_dev *ndev, u64 db_bits, void __iomem *mmio) argument
296 ndev_spad_read(struct intel_ntb_dev *ndev, int idx, void __iomem *mmio) argument
308 ndev_spad_write(struct intel_ntb_dev *ndev, int idx, u32 val, void __iomem *mmio) argument
496 void __iomem *mmio; local
848 void __iomem *mmio; local
1208 xeon_db_ioread(const void __iomem *mmio) argument
1213 xeon_db_iowrite(u64 bits, void __iomem *mmio) argument
1296 void __iomem *mmio; local
[all...]
/linux-master/drivers/ntb/hw/amd/
H A Dntb_hw_amd.h66 static inline u64 _read64(void __iomem *mmio) argument
70 low = readl(mmio);
71 high = readl(mmio + sizeof(u32));
82 static inline void _write64(u64 val, void __iomem *mmio) argument
84 writel(val, mmio);
85 writel(val >> 32, mmio + sizeof(u32));
/linux-master/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c63 reg->d = readq(this->mmio);
65 reg->w[0] = readl(this->mmio);
66 reg->w[1] = readl(this->mmio + 4);
145 iounmap(this->mmio);
157 this->mmio = ioremap(this->reg_base, this->reg_size);
158 if (IS_ERR_OR_NULL(this->mmio))
H A Dlsdc_gfxpll.h37 void __iomem *mmio; member in struct:loongson_gfxpll
H A Dlsdc_pixpll.h77 void __iomem *mmio; member in struct:lsdc_pixpll
/linux-master/drivers/net/ethernet/mediatek/
H A Dmtk_wed_wo.c25 if (regmap_read(wo->mmio.regs, reg, &val))
34 regmap_write(wo->mmio.regs, reg, val);
62 spin_lock_irqsave(&wo->mmio.lock, flags);
63 wo->mmio.irq_mask &= ~mask;
64 wo->mmio.irq_mask |= val;
66 mtk_wed_wo_set_isr(wo, wo->mmio.irq_mask);
67 spin_unlock_irqrestore(&wo->mmio.lock, flags);
74 tasklet_schedule(&wo->mmio.irq_tasklet);
230 tasklet_schedule(&wo->mmio.irq_tasklet);
237 struct mtk_wed_wo *wo = from_tasklet(wo, t, mmio
[all...]
/linux-master/drivers/hid/amd-sfh-hid/sfh1_1/
H A Damd_sfh_interface.c23 if (!readl_poll_timeout(mp2->mmio + amd_get_p2c_val(mp2, 0), cmd_resp.resp,
42 writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0));
55 writeq(0x0, privdata->mmio + amd_get_c2p_val(privdata, 1));
56 writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0));
69 writel(cmd_base.ul, privdata->mmio + amd_get_c2p_val(privdata, 0));
100 hpdstatus.val = readl(emp2->mmio + AMD_C2P_MSG(4));
/linux-master/drivers/comedi/
H A Dcomedi_pci.c96 * and have no ioremapped regions other than that pointed to by @dev->mmio may
101 * Free the IRQ if @dev->irq is non-zero, iounmap @dev->mmio if it is
116 if (dev->mmio) {
117 iounmap(dev->mmio);
118 dev->mmio = NULL;
/linux-master/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_drv.h101 void __iomem *mmio; member in struct:rcar_du_device
142 return ioread32(rcdu->mmio + reg);
147 iowrite32(data, rcdu->mmio + reg);
/linux-master/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dtegra.h54 bool detect, bool mmio, u64 subdev_mask,
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dpriv.h15 u32 (*mmio)(struct nvkm_devinit *, u32); member in struct:nvkm_devinit_func
/linux-master/drivers/gpu/drm/renesas/shmobile/
H A Dshmob_drm_drv.h33 void __iomem *mmio; member in struct:shmob_drm_device
/linux-master/drivers/gpu/drm/renesas/rz-du/
H A Drzg2l_du_drv.h61 void __iomem *mmio; member in struct:rzg2l_du_device

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