/linux-master/drivers/clk/imx/ |
H A D | clk-imx8mm.c | 303 void __iomem *base; local 323 base = of_iomap(np, 0); 325 if (WARN_ON(!base)) 328 hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 329 hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 330 hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 331 hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 332 hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 333 hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 334 hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base [all...] |
H A D | clk-imx7ulp.c | 50 void __iomem *base; local 69 base = of_iomap(np, 0); 70 WARN_ON(!base); 73 hws[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); 74 hws[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE); 77 hws[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x508, 8, 3, CLK_SET_RATE_GATE); 78 hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608, 8, 3, CLK_SET_RATE_GATE); 80 /* name parent_name base */ 81 hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "apll", "apll_pre_div", base + 0x500); 82 hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "spll", "spll_pre_div", base 139 void __iomem *base; local 187 void __iomem *base; local 234 void __iomem *base; local [all...] |
H A D | clk-imx8mn.c | 323 void __iomem *base; local 343 base = devm_of_iomap(dev, np, 0, NULL); 345 if (WARN_ON(IS_ERR(base))) { 346 ret = PTR_ERR(base); 350 hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 351 hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 352 hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 353 hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 354 hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); 355 hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base [all...] |
H A D | clk-imx35.c | 86 void __iomem *base; local 91 base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K); 92 BUG_ON(!base); 94 pdr0 = __raw_readl(base + MXC_CCM_PDR0); 108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); 109 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); 134 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); 135 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); 136 clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel)); 138 clk[uart_sel] = imx_clk_mux("uart_sel", base [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/ |
H A D | busnv04.c | 24 #define nv04_i2c_bus(p) container_of((p), struct nv04_i2c_bus, base) 30 struct nvkm_i2c_bus base; member in struct:nv04_i2c_bus 36 nv04_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) argument 38 struct nv04_i2c_bus *bus = nv04_i2c_bus(base); 39 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; 47 nv04_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) argument 49 struct nv04_i2c_bus *bus = nv04_i2c_bus(base); 50 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; 58 nv04_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) argument 60 struct nv04_i2c_bus *bus = nv04_i2c_bus(base); 66 nv04_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) argument [all...] |
H A D | busnv4e.c | 24 #define nv4e_i2c_bus(p) container_of((p), struct nv4e_i2c_bus, base) 28 struct nvkm_i2c_bus base; member in struct:nv4e_i2c_bus 33 nv4e_i2c_bus_drive_scl(struct nvkm_i2c_bus *base, int state) argument 35 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); 36 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; 41 nv4e_i2c_bus_drive_sda(struct nvkm_i2c_bus *base, int state) argument 43 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); 44 struct nvkm_device *device = bus->base.pad->i2c->subdev.device; 49 nv4e_i2c_bus_sense_scl(struct nvkm_i2c_bus *base) argument 51 struct nv4e_i2c_bus *bus = nv4e_i2c_bus(base); 57 nv4e_i2c_bus_sense_sda(struct nvkm_i2c_bus *base) argument [all...] |
/linux-master/include/linux/soc/actions/ |
H A D | owl-sps.h | 9 int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable);
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/ |
H A D | dcn31_panel_cntl.h | 33 struct panel_cntl base; member in struct:dcn31_panel_cntl
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/linux-master/include/linux/platform_data/ |
H A D | clk-fch.h | 14 void __iomem *base; member in struct:fch_clk_data
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/linux-master/arch/riscv/include/asm/ |
H A D | vdso.h | 22 #define VDSO_SYMBOL(base, name) \ 23 (void __user *)((unsigned long)(base) + __vdso_##name##_offset) 28 #define COMPAT_VDSO_SYMBOL(base, name) \ 29 (void __user *)((unsigned long)(base) + compat__vdso_##name##_offset)
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/linux-master/drivers/gpu/drm/arm/display/include/ |
H A D | malidp_io.h | 13 malidp_read32(u32 __iomem *base, u32 offset) argument 15 return readl((base + (offset >> 2))); 19 malidp_write32(u32 __iomem *base, u32 offset, u32 v) argument 21 writel(v, (base + (offset >> 2))); 25 malidp_write64(u32 __iomem *base, u32 offset, u64 v) argument 27 writel(lower_32_bits(v), (base + (offset >> 2))); 28 writel(upper_32_bits(v), (base + (offset >> 2) + 1)); 32 malidp_write32_mask(u32 __iomem *base, u32 offset, u32 m, u32 v) argument 34 u32 tmp = malidp_read32(base, offset); 37 malidp_write32(base, offse 41 malidp_write_group(u32 __iomem *base, u32 offset, int num, const u32 *values) argument [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
H A D | gf100.h | 4 #define gf100_fb(p) container_of((p), struct gf100_fb, base) 8 struct nvkm_fb base; member in struct:gf100_fb 17 void gm200_fb_init(struct nvkm_fb *base);
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H A D | rammcp77.c | 24 #define mcp77_ram(p) container_of((p), struct mcp77_ram, base) 28 struct nvkm_ram base; member in struct:mcp77_ram 33 mcp77_ram_init(struct nvkm_ram *base) argument 35 struct mcp77_ram *ram = mcp77_ram(base); 36 struct nvkm_device *device = ram->base.fb->subdev.device; 37 u32 dniso = ((ram->base.size - (ram->poller_base + 0x00)) >> 5) - 1; 38 u32 hostnb = ((ram->base.size - (ram->poller_base + 0x20)) >> 5) - 1; 39 u32 flush = ((ram->base.size - (ram->poller_base + 0x40)) >> 5) - 1; 64 u64 base = (u64)nvkm_rd32(device, 0x100e10) << 12; local 71 *pram = &ram->base; [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/ |
H A D | nv40.c | 24 #define nv40_instmem(p) container_of((p), struct nv40_instmem, base) 31 struct nvkm_instmem base; member in struct:nv40_instmem 39 #define nv40_instobj(p) container_of((p), struct nv40_instobj, base.memory) 42 struct nvkm_instobj base; member in struct:nv40_instobj 102 mutex_lock(&iobj->imem->base.mutex); 104 mutex_unlock(&iobj->imem->base.mutex); 105 nvkm_instobj_dtor(&iobj->imem->base, &iobj->base); 120 nv40_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, argument 123 struct nv40_instmem *imem = nv40_instmem(base); 146 nv40_instmem_rd32(struct nvkm_instmem *base, u32 addr) argument 152 nv40_instmem_wr32(struct nvkm_instmem *base, u32 addr, u32 data) argument 158 nv40_instmem_oneinit(struct nvkm_instmem *base) argument 214 nv40_instmem_dtor(struct nvkm_instmem *base) argument [all...] |
/linux-master/drivers/media/pci/ddbridge/ |
H A D | ddbridge-mci.c | 18 struct ddb_link *link = state->base->link; 44 struct ddb_link *link = state->base->link; 56 struct ddb_link *link = state->base->link; 69 stat = wait_for_completion_timeout(&state->base->completion, HZ); 71 dev_warn(state->base->dev, "MCI-%d: MCI timeout\n", state->nr); 86 mutex_lock(&state->base->mci_lock); 90 mutex_unlock(&state->base->mci_lock); 96 struct mci_base *base = (struct mci_base *)priv; local 98 complete(&base->completion); 124 struct mci_base *base; local [all...] |
/linux-master/drivers/phy/mediatek/ |
H A D | phy-mtk-mipi-dsi-mt8183.c | 50 void __iomem *base = mipi_tx->regs; local 75 mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS); 77 mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); 78 mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); 80 mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); 82 writel(pcw, base + MIPITX_PLL_CON0); 83 mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0); 84 mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN); 92 void __iomem *base = mipi_tx->regs; local 94 mtk_phy_clear_bits(base 135 void __iomem *base = mipi_tx->regs; local 160 void __iomem *base = mipi_tx->regs; local [all...] |
/linux-master/drivers/gpu/drm/i915/gem/ |
H A D | i915_gem_clflush.c | 17 struct dma_fence_work base; member in struct:clflush 29 static void clflush_work(struct dma_fence_work *base) argument 31 struct clflush *clflush = container_of(base, typeof(*clflush), base); 36 static void clflush_release(struct dma_fence_work *base) argument 38 struct clflush *clflush = container_of(base, typeof(*clflush), base); 65 dma_fence_work_init(&clflush->base, &clflush_ops); 74 struct drm_i915_private *i915 = to_i915(obj->base.dev); 112 dma_resv_reserve_fences(obj->base [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn301/ |
H A D | dcn301_dio_link_encoder.c | 36 enc10->base.ctx 38 enc10->base.ctx->logger 93 enc10->base.funcs = &dcn301_link_enc_funcs; 94 enc10->base.ctx = init_data->ctx; 95 enc10->base.id = init_data->encoder; 97 enc10->base.hpd_source = init_data->hpd_source; 98 enc10->base.connector = init_data->connector; 100 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 102 enc10->base.features = *enc_features; 104 enc10->base [all...] |
/linux-master/arch/mips/loongson2ef/common/ |
H A D | init.c | 16 /* Loongson CPU address windows config space base address */ 21 void *base; local 23 base = (void *)(CAC_BASE + 0x380); 24 memcpy(base, except_vec_nmi, 0x80); 25 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 39 /* init base address of io space */ 44 /*init the uart base address */
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/linux-master/drivers/nvmem/ |
H A D | bcm-ocotp.c | 72 void __iomem *base; member in struct:otpc_priv 77 static inline void set_command(void __iomem *base, u32 command) argument 79 writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET); 82 static inline void set_cpu_address(void __iomem *base, u32 addr) argument 84 writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET); 87 static inline void set_start_bit(void __iomem *base) argument 89 writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET); 92 static inline void reset_start_bit(void __iomem *base) argument 94 writel(0, base + OTPC_CMD_START_OFFSET); 97 static inline void write_cpu_data(void __iomem *base, u3 argument 102 poll_cpu_status(void __iomem *base, u32 value) argument 119 enable_ocotp_program(void __iomem *base) argument 139 disable_ocotp_program(void __iomem *base) argument [all...] |
/linux-master/drivers/phy/marvell/ |
H A D | phy-pxa-usb.c | 117 void __iomem *base; member in struct:pxa_usb_phy 125 static unsigned int u2o_get(void __iomem *base, unsigned int offset) argument 127 return readl_relaxed(base + offset); 130 static void u2o_set(void __iomem *base, unsigned int offset, argument 135 reg = readl_relaxed(base + offset); 137 writel_relaxed(reg, base + offset); 138 readl_relaxed(base + offset); 141 static void u2o_clear(void __iomem *base, unsigned int offset, argument 146 reg = readl_relaxed(base + offset); 148 writel_relaxed(reg, base 152 u2o_write(void __iomem *base, unsigned int offset, unsigned int value) argument 162 void __iomem *base = pxa_usb_phy->base; local 249 void __iomem *base = pxa_usb_phy->base; local [all...] |
/linux-master/drivers/s390/block/ |
H A D | dasd_ioctl.c | 41 struct dasd_device *base; local 46 base = dasd_device_from_gendisk(bdev->bd_disk); 47 if (!base) 50 dasd_enable_device(base); 51 dasd_put_device(base); 62 struct dasd_device *base; local 67 base = dasd_device_from_gendisk(bdev->bd_disk); 68 if (!base) 78 dasd_set_target_state(base, DASD_STATE_BASIC); 84 dasd_put_device(base); 94 struct dasd_device *base; local 115 struct dasd_device *base; local 138 struct dasd_device *base; local 173 struct dasd_device *base; local 194 struct dasd_device *base; local 232 struct dasd_device *base; local 252 struct dasd_device *base; local 290 struct dasd_device *base; local 341 struct dasd_device *base; local 503 struct dasd_device *base; local 579 struct dasd_device *base; local 614 struct dasd_device *base; local 715 struct dasd_device *base; local [all...] |
/linux-master/drivers/net/ethernet/broadcom/bnx2x/ |
H A D | bnx2x_fw_defs.h | 15 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base) 17 (IRO[151].base + ((assertListEntry) * IRO[151].m1)) 19 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \ 22 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \ 25 (IRO[163].base + ((funcId) * IRO[163].m1)) 27 (IRO[153].base + ((funcId) * IRO[153].m1)) 29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2)) 31 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \ 33 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base) 35 (IRO[324].base [all...] |
/linux-master/drivers/usb/host/ |
H A D | xhci-mvebu.c | 22 static void xhci_mvebu_mbus_config(void __iomem *base, argument 29 writel(0, base + USB3_WIN_CTRL(win)); 30 writel(0, base + USB3_WIN_BASE(win)); 39 base + USB3_WIN_CTRL(win)); 41 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(win)); 50 void __iomem *base; local 61 base = ioremap(res->start, resource_size(res)); 62 if (!base) 66 xhci_mvebu_mbus_config(base, dra [all...] |
/linux-master/drivers/platform/mips/ |
H A D | ls2k-reset.c | 15 static void __iomem *base; variable 19 writel(0x1, base + RST_CNT); 25 writel((readl(base + PM1_STS) & 0xffffffff), base + PM1_STS); 27 writel(GENMASK(12, 10) | BIT(13), base + PM1_CNT); 40 base = of_iomap(np, 0); 42 if (!base) { 43 pr_info("Failed to map PM register base address\n");
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