1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (C) 2016 Broadcom
3
4#include <linux/acpi.h>
5#include <linux/delay.h>
6#include <linux/device.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/nvmem-provider.h>
10#include <linux/of.h>
11#include <linux/platform_device.h>
12
13/*
14 * # of tries for OTP Status. The time to execute a command varies. The slowest
15 * commands are writes which also vary based on the # of bits turned on. Writing
16 * 0xffffffff takes ~3800 us.
17 */
18#define OTPC_RETRIES                 5000
19
20/* Sequence to enable OTP program */
21#define OTPC_PROG_EN_SEQ             { 0xf, 0x4, 0x8, 0xd }
22
23/* OTPC Commands */
24#define OTPC_CMD_READ                0x0
25#define OTPC_CMD_OTP_PROG_ENABLE     0x2
26#define OTPC_CMD_OTP_PROG_DISABLE    0x3
27#define OTPC_CMD_PROGRAM             0x8
28
29/* OTPC Status Bits */
30#define OTPC_STAT_CMD_DONE           BIT(1)
31#define OTPC_STAT_PROG_OK            BIT(2)
32
33/* OTPC register definition */
34#define OTPC_MODE_REG_OFFSET         0x0
35#define OTPC_MODE_REG_OTPC_MODE      0
36#define OTPC_COMMAND_OFFSET          0x4
37#define OTPC_COMMAND_COMMAND_WIDTH   6
38#define OTPC_CMD_START_OFFSET        0x8
39#define OTPC_CMD_START_START         0
40#define OTPC_CPU_STATUS_OFFSET       0xc
41#define OTPC_CPUADDR_REG_OFFSET      0x28
42#define OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH 16
43#define OTPC_CPU_WRITE_REG_OFFSET    0x2c
44
45#define OTPC_CMD_MASK  (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
46#define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)
47
48
49struct otpc_map {
50	/* in words. */
51	u32 otpc_row_size;
52	/* 128 bit row / 4 words support. */
53	u16 data_r_offset[4];
54	/* 128 bit row / 4 words support. */
55	u16 data_w_offset[4];
56};
57
58static struct otpc_map otp_map = {
59	.otpc_row_size = 1,
60	.data_r_offset = {0x10},
61	.data_w_offset = {0x2c},
62};
63
64static struct otpc_map otp_map_v2 = {
65	.otpc_row_size = 2,
66	.data_r_offset = {0x10, 0x5c},
67	.data_w_offset = {0x2c, 0x64},
68};
69
70struct otpc_priv {
71	struct device *dev;
72	void __iomem *base;
73	const struct otpc_map *map;
74	struct nvmem_config *config;
75};
76
77static inline void set_command(void __iomem *base, u32 command)
78{
79	writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET);
80}
81
82static inline void set_cpu_address(void __iomem *base, u32 addr)
83{
84	writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET);
85}
86
87static inline void set_start_bit(void __iomem *base)
88{
89	writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET);
90}
91
92static inline void reset_start_bit(void __iomem *base)
93{
94	writel(0, base + OTPC_CMD_START_OFFSET);
95}
96
97static inline void write_cpu_data(void __iomem *base, u32 value)
98{
99	writel(value, base + OTPC_CPU_WRITE_REG_OFFSET);
100}
101
102static int poll_cpu_status(void __iomem *base, u32 value)
103{
104	u32 status;
105	u32 retries;
106
107	for (retries = 0; retries < OTPC_RETRIES; retries++) {
108		status = readl(base + OTPC_CPU_STATUS_OFFSET);
109		if (status & value)
110			break;
111		udelay(1);
112	}
113	if (retries == OTPC_RETRIES)
114		return -EAGAIN;
115
116	return 0;
117}
118
119static int enable_ocotp_program(void __iomem *base)
120{
121	static const u32 vals[] = OTPC_PROG_EN_SEQ;
122	int i;
123	int ret;
124
125	/* Write the magic sequence to enable programming */
126	set_command(base, OTPC_CMD_OTP_PROG_ENABLE);
127	for (i = 0; i < ARRAY_SIZE(vals); i++) {
128		write_cpu_data(base, vals[i]);
129		set_start_bit(base);
130		ret = poll_cpu_status(base, OTPC_STAT_CMD_DONE);
131		reset_start_bit(base);
132		if (ret)
133			return ret;
134	}
135
136	return poll_cpu_status(base, OTPC_STAT_PROG_OK);
137}
138
139static int disable_ocotp_program(void __iomem *base)
140{
141	int ret;
142
143	set_command(base, OTPC_CMD_OTP_PROG_DISABLE);
144	set_start_bit(base);
145	ret = poll_cpu_status(base, OTPC_STAT_PROG_OK);
146	reset_start_bit(base);
147
148	return ret;
149}
150
151static int bcm_otpc_read(void *context, unsigned int offset, void *val,
152	size_t bytes)
153{
154	struct otpc_priv *priv = context;
155	u32 *buf = val;
156	u32 bytes_read;
157	u32 address = offset / priv->config->word_size;
158	int i, ret;
159
160	for (bytes_read = 0; bytes_read < bytes;) {
161		set_command(priv->base, OTPC_CMD_READ);
162		set_cpu_address(priv->base, address++);
163		set_start_bit(priv->base);
164		ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
165		if (ret) {
166			dev_err(priv->dev, "otp read error: 0x%x", ret);
167			return -EIO;
168		}
169
170		for (i = 0; i < priv->map->otpc_row_size; i++) {
171			*buf++ = readl(priv->base +
172					priv->map->data_r_offset[i]);
173			bytes_read += sizeof(*buf);
174		}
175
176		reset_start_bit(priv->base);
177	}
178
179	return 0;
180}
181
182static int bcm_otpc_write(void *context, unsigned int offset, void *val,
183	size_t bytes)
184{
185	struct otpc_priv *priv = context;
186	u32 *buf = val;
187	u32 bytes_written;
188	u32 address = offset / priv->config->word_size;
189	int i, ret;
190
191	if (offset % priv->config->word_size)
192		return -EINVAL;
193
194	ret = enable_ocotp_program(priv->base);
195	if (ret)
196		return -EIO;
197
198	for (bytes_written = 0; bytes_written < bytes;) {
199		set_command(priv->base, OTPC_CMD_PROGRAM);
200		set_cpu_address(priv->base, address++);
201		for (i = 0; i < priv->map->otpc_row_size; i++) {
202			writel(*buf, priv->base + priv->map->data_w_offset[i]);
203			buf++;
204			bytes_written += sizeof(*buf);
205		}
206		set_start_bit(priv->base);
207		ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
208		reset_start_bit(priv->base);
209		if (ret) {
210			dev_err(priv->dev, "otp write error: 0x%x", ret);
211			return -EIO;
212		}
213	}
214
215	disable_ocotp_program(priv->base);
216
217	return 0;
218}
219
220static struct nvmem_config bcm_otpc_nvmem_config = {
221	.name = "bcm-ocotp",
222	.read_only = false,
223	.word_size = 4,
224	.stride = 4,
225	.reg_read = bcm_otpc_read,
226	.reg_write = bcm_otpc_write,
227};
228
229static const struct of_device_id bcm_otpc_dt_ids[] = {
230	{ .compatible = "brcm,ocotp", .data = &otp_map },
231	{ .compatible = "brcm,ocotp-v2", .data = &otp_map_v2 },
232	{ },
233};
234MODULE_DEVICE_TABLE(of, bcm_otpc_dt_ids);
235
236static const struct acpi_device_id bcm_otpc_acpi_ids[] __maybe_unused = {
237	{ .id = "BRCM0700", .driver_data = (kernel_ulong_t)&otp_map },
238	{ .id = "BRCM0701", .driver_data = (kernel_ulong_t)&otp_map_v2 },
239	{ /* sentinel */ }
240};
241MODULE_DEVICE_TABLE(acpi, bcm_otpc_acpi_ids);
242
243static int bcm_otpc_probe(struct platform_device *pdev)
244{
245	struct device *dev = &pdev->dev;
246	struct otpc_priv *priv;
247	struct nvmem_device *nvmem;
248	int err;
249	u32 num_words;
250
251	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
252	if (!priv)
253		return -ENOMEM;
254
255	priv->map = device_get_match_data(dev);
256	if (!priv->map)
257		return -ENODEV;
258
259	/* Get OTP base address register. */
260	priv->base = devm_platform_ioremap_resource(pdev, 0);
261	if (IS_ERR(priv->base)) {
262		dev_err(dev, "unable to map I/O memory\n");
263		return PTR_ERR(priv->base);
264	}
265
266	/* Enable CPU access to OTPC. */
267	writel(readl(priv->base + OTPC_MODE_REG_OFFSET) |
268		BIT(OTPC_MODE_REG_OTPC_MODE),
269		priv->base + OTPC_MODE_REG_OFFSET);
270	reset_start_bit(priv->base);
271
272	/* Read size of memory in words. */
273	err = device_property_read_u32(dev, "brcm,ocotp-size", &num_words);
274	if (err) {
275		dev_err(dev, "size parameter not specified\n");
276		return -EINVAL;
277	} else if (num_words == 0) {
278		dev_err(dev, "size must be > 0\n");
279		return -EINVAL;
280	}
281
282	bcm_otpc_nvmem_config.size = 4 * num_words;
283	bcm_otpc_nvmem_config.dev = dev;
284	bcm_otpc_nvmem_config.priv = priv;
285
286	if (priv->map == &otp_map_v2) {
287		bcm_otpc_nvmem_config.word_size = 8;
288		bcm_otpc_nvmem_config.stride = 8;
289	}
290
291	priv->config = &bcm_otpc_nvmem_config;
292
293	nvmem = devm_nvmem_register(dev, &bcm_otpc_nvmem_config);
294	if (IS_ERR(nvmem)) {
295		dev_err(dev, "error registering nvmem config\n");
296		return PTR_ERR(nvmem);
297	}
298
299	return 0;
300}
301
302static struct platform_driver bcm_otpc_driver = {
303	.probe	= bcm_otpc_probe,
304	.driver = {
305		.name	= "brcm-otpc",
306		.of_match_table = bcm_otpc_dt_ids,
307		.acpi_match_table = ACPI_PTR(bcm_otpc_acpi_ids),
308	},
309};
310module_platform_driver(bcm_otpc_driver);
311
312MODULE_DESCRIPTION("Broadcom OTPC driver");
313MODULE_LICENSE("GPL v2");
314