Searched refs:bank (Results 76 - 100 of 367) sorted by relevance

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/linux-master/drivers/memory/samsung/
H A Dexynos-srom.c70 u32 bank, width, pmc = 0; local
74 if (of_property_read_u32(np, "reg", &bank))
84 bank *= 4; /* Convert bank into shift/offset */
91 bw = (bw & ~(EXYNOS_SROM_BW__CS_MASK << bank)) | (cs << bank);
100 srom->reg_base + EXYNOS_SROM_BC0 + bank);
142 "Could not decode bank configuration for %pOFn\n",
149 * If any bank failed to configure, we still provide suspend/resume,
/linux-master/drivers/hwspinlock/
H A Dsun6i_hwspinlock.c30 struct hwspinlock_device *bank; member in struct:sun6i_hwspinlock_data
157 priv->bank = devm_kzalloc(&pdev->dev, struct_size(priv->bank, lock, priv->nlocks),
159 if (!priv->bank) {
165 hwlock = &priv->bank->lock[i];
182 return devm_hwspin_lock_register(&pdev->dev, priv->bank, &sun6i_hwspinlock_ops,
H A Dsprd_hwspinlock.c36 struct hwspinlock_device bank; member in struct:sprd_hwspinlock_dev
43 dev_get_drvdata(lock->bank->dev);
53 dev_warn(sprd_hwlock->bank.dev,
96 struct_size(sprd_hwlock, bank.lock, SPRD_HWLOCKS_NUM),
127 lock = &sprd_hwlock->bank.lock[i];
133 return devm_hwspin_lock_register(&pdev->dev, &sprd_hwlock->bank,
H A Dqcom_hwspinlock.c179 struct hwspinlock_device *bank; local
195 bank = devm_kzalloc(&pdev->dev, sizeof(*bank) + array_size, GFP_KERNEL);
196 if (!bank)
199 platform_set_drvdata(pdev, bank);
206 bank->lock[i].priv = devm_regmap_field_alloc(&pdev->dev,
208 if (IS_ERR(bank->lock[i].priv))
209 return PTR_ERR(bank->lock[i].priv);
212 return devm_hwspin_lock_register(&pdev->dev, bank, &qcom_hwspinlock_ops,
/linux-master/drivers/hwmon/
H A Dnct6775-i2c.c14 * bank-select register (which seems, thankfully, to be replicated for the i2c
32 u8 bank = reg >> 8; local
36 if (bank != data->bank) {
37 ret = i2c_smbus_write_byte_data(client, NCT6775_REG_BANK, bank);
40 data->bank = bank;
71 * This is a lie, but writing anything but the bank-select register is
/linux-master/drivers/mtd/devices/
H A Dspear_smi.c184 * @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
188 * @num_parts: Total number of partition in each bank of NOR-flash.
189 * @parts: Partition info for each bank of NOR-flash.
196 u32 bank; member in struct:spear_snor_flash
216 * @bank: bank to which flash is connected
219 * given bank.
221 static int spear_smi_read_sr(struct spear_smi *dev, u32 bank) argument
234 writel((bank << BANK_SHIFT) | RD_STATUS_REG | TFIE,
258 * @bank
264 spear_smi_wait_till_ready(struct spear_smi *dev, u32 bank, unsigned long timeout) argument
379 spear_smi_write_enable(struct spear_smi *dev, u32 bank) argument
444 spear_smi_erase_sector(struct spear_smi *dev, u32 bank, u32 command, u32 bytes) argument
498 u32 addr, command, bank; local
615 spear_smi_cpy_toio(struct spear_smi *dev, u32 bank, void __iomem *dest, const void *src, size_t len) argument
745 spear_smi_probe_flash(struct spear_smi *dev, u32 bank) argument
841 spear_smi_setup_banks(struct platform_device *pdev, u32 bank, struct device_node *np) argument
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/linux-master/drivers/pinctrl/nuvoton/
H A Dpinctrl-npcm8xx.c140 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); local
143 ioread32(bank->base + NPCM8XX_GP_N_DIN),
144 ioread32(bank->base + NPCM8XX_GP_N_DOUT),
145 ioread32(bank->base + NPCM8XX_GP_N_IEM),
146 ioread32(bank->base + NPCM8XX_GP_N_OE));
148 ioread32(bank->base + NPCM8XX_GP_N_PU),
149 ioread32(bank->base + NPCM8XX_GP_N_PD),
150 ioread32(bank->base + NPCM8XX_GP_N_DBNC),
151 ioread32(bank->base + NPCM8XX_GP_N_POL));
153 ioread32(bank
173 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); local
186 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); local
198 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); local
211 struct npcm8xx_gpio *bank; local
230 struct npcm8xx_gpio *bank = local
269 struct npcm8xx_gpio *bank = local
278 struct npcm8xx_gpio *bank = local
287 struct npcm8xx_gpio *bank = local
1859 npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank, struct regmap *gcr_regmap, unsigned int pin) argument
1877 npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank, struct regmap *gcr_regmap, unsigned int pin, int arg) argument
1920 struct npcm8xx_gpio *bank = local
1941 struct npcm8xx_gpio *bank = local
2072 struct npcm8xx_gpio *bank = local
2094 debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio, u32 nanosecs) argument
2163 struct npcm8xx_gpio *bank = local
2190 struct npcm8xx_gpio *bank = local
2252 struct npcm8xx_gpio *bank = local
2331 struct npcm8xx_gpio *bank = gpiochip_get_data(chip); local
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/linux-master/include/trace/events/
H A Dmce.h34 __field( u8, bank )
54 __entry->bank = m->bank;
61 __entry->bank, __entry->status,
/linux-master/arch/x86/events/amd/
H A Diommu.c158 u32 shift, bank, cntr; local
164 for (bank = 0; bank < max_banks; bank++) {
166 shift = bank + (bank*3) + cntr;
171 event->hw.iommu_bank = bank;
185 u8 bank, u8 cntr)
194 if ((bank > max_banks) || (cntr > max_cntrs))
197 shift = bank
184 clear_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu, u8 bank, u8 cntr) argument
241 u8 bank = hwc->iommu_bank; local
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/linux-master/drivers/gpio/
H A Dgpio-ep93xx.c38 * Static mapping of GPIO bank F IRQS:
127 * between bank A and B and each has their own gpiochip.
348 struct ep93xx_gpio_bank *bank)
350 void __iomem *data = epg->base + bank->data;
351 void __iomem *dir = epg->base + bank->dir;
361 gc->label = bank->label;
362 gc->base = bank->base;
365 if (bank->has_irq || bank->has_hierarchical_irq) {
372 egc->eic->irq_offset = bank
345 ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, struct platform_device *pdev, struct ep93xx_gpio *epg, struct ep93xx_gpio_bank *bank) argument
441 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; local
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H A Dgpio-74x164.c44 u8 bank = chip->registers - 1 - offset / 8; local
49 ret = (chip->buffer[bank] >> pin) & 0x1;
59 u8 bank = chip->registers - 1 - offset / 8; local
64 chip->buffer[bank] |= (1 << pin);
66 chip->buffer[bank] &= ~(1 << pin);
78 size_t bank; local
83 bank = chip->registers - 1 - offset / 8;
86 chip->buffer[bank] &= ~bankmask;
87 chip->buffer[bank] |= bitmask;
H A Dgpio-uniphier.c35 static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank) argument
39 reg = (bank + 1) * 8;
52 unsigned int *bank, u32 *mask)
54 *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
72 static void uniphier_gpio_bank_write(struct gpio_chip *chip, unsigned int bank, argument
80 uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
88 unsigned int bank; local
91 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
93 uniphier_gpio_bank_write(chip, bank, reg, mask, val ? mask : 0);
100 unsigned int bank, reg_offse local
51 uniphier_gpio_get_bank_and_mask(unsigned int offset, unsigned int *bank, u32 *mask) argument
149 unsigned long i, bank, bank_mask, bank_bits; local
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/linux-master/include/sound/
H A Dump_convert.h31 struct ump_cvt_to_ump_bank bank[16]; /* per channel */ member in struct:ump_cvt_to_ump
/linux-master/drivers/mtd/nand/raw/
H A Dfsl_elbc_nand.c41 int bank; /* Chip select bank number */ member in struct:fsl_elbc_mtd
191 dev_vdbg(priv->dev, "set_addr: bank=%d, "
220 "fbcr=%08x bank=%d\n",
222 in_be32(&lbc->fbcr), priv->bank);
226 out_be32(&lbc->lsor, priv->bank);
533 * chips per bank.
687 dev_dbg(priv->dev, "eLBC Set Information for bank %d\n", priv->bank);
695 if (in_be32(&lbc->bank[pri
866 int bank; local
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/linux-master/drivers/iommu/
H A Dmtk_iommu.c230 * The IOMMU HW may have 5 banks. Each bank has a independent pgtable.
231 * Here list how many banks this SoC supports/enables and which ports are in which bank.
249 struct mtk_iommu_domain *m4u_dom; /* Each bank has a domain */
264 struct mtk_iommu_bank_data *bank; member in struct:mtk_iommu_data
284 struct mtk_iommu_bank_data *bank; member in struct:mtk_iommu_domain
378 struct mtk_iommu_bank_data *bank = &data->bank[0]; local
379 void __iomem *base = bank->base;
382 spin_lock_irqsave(&bank->tlb_lock, flags);
386 spin_unlock_irqrestore(&bank
389 mtk_iommu_tlb_flush_range_sync(unsigned long iova, size_t size, struct mtk_iommu_bank_data *bank) argument
457 struct mtk_iommu_bank_data *bank = dev_id; local
715 struct mtk_iommu_bank_data *bank; local
1258 struct mtk_iommu_bank_data *bank; local
1415 struct mtk_iommu_bank_data *bank; local
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/linux-master/arch/arm/mach-omap2/
H A Dpowerdomain.c653 * @bank: memory bank number to set (0-3)
656 * Set the next power state @pwrst that memory bank @bank of the
658 * state. @bank will be a number from 0 to 3, and represents different
661 * supported for this memory bank, -EEXIST if the target memory
662 * bank does not exist or is not controllable, or returns 0 upon
665 int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) argument
672 if (pwrdm->banks < (bank + 1))
675 if (!(pwrdm->pwrsts_mem_on[bank]
703 pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) argument
799 pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) argument
829 pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) argument
858 pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) argument
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H A Dprm33xx.c224 static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, argument
229 m = pwrdm->mem_on_mask[bank];
239 static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, argument
244 m = pwrdm->mem_ret_mask[bank];
254 static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) argument
258 m = pwrdm->mem_pwrst_mask[bank];
269 static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) argument
273 m = pwrdm->mem_retst_mask[bank];
/linux-master/drivers/infiniband/hw/hns/
H A Dhns_roce_cq.c40 static u8 get_least_load_bankid_for_cq(struct hns_roce_bank *bank) argument
42 u32 least_load = bank[0].inuse;
48 bankcnt = bank[i].inuse;
61 struct hns_roce_bank *bank; local
66 bankid = get_least_load_bankid_for_cq(cq_table->bank);
67 bank = &cq_table->bank[bankid];
69 id = ida_alloc_range(&bank->ida, bank->min, bank
92 struct hns_roce_bank *bank; local
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/linux-master/drivers/pinctrl/freescale/
H A Dpinctrl-mxs.h17 #define PINID(bank, pin) ((bank) * 32 + (pin))
22 * bank: 15..12 (4)
/linux-master/arch/arm/mach-omap1/
H A Dirq.c10 * Completely re-written to support various OMAP chips with bank specific
69 static inline unsigned int irq_bank_readl(int bank, int offset) argument
71 return readl_relaxed(irq_banks[bank].va + offset);
73 static inline void irq_bank_writel(unsigned long value, int bank, int offset) argument
75 writel_relaxed(value, irq_banks[bank].va + offset);
103 signed int bank; local
106 bank = IRQ_BANK(irq);
107 /* FIQ is only available on bank 0 interrupts */
108 fiq = bank ? 0 : (fiq & 0x1);
111 irq_bank_writel(val, bank, offse
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/linux-master/include/linux/
H A Damd-iommu.h82 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
84 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
/linux-master/arch/um/drivers/
H A Dpty.c81 char *pty, *bank, *cp; local
85 for (bank = "pqrs"; *bank; bank++) {
86 line[strlen("/dev/pty")] = *bank;
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dadf_hw_arbiter.c50 struct adf_accel_dev *accel_dev = ring->bank->accel_dev;
65 arben_tx = (ring->bank->ring_mask & tx_ring_mask) >> 0;
66 arben_rx = (ring->bank->ring_mask & rx_ring_mask) >> shift;
69 csr_ops->write_csr_ring_srv_arb_en(ring->bank->csr_addr,
70 ring->bank->bank_number, arben);
/linux-master/drivers/reset/
H A Dreset-simple.c35 int bank = id / (reg_width * BITS_PER_BYTE); local
42 reg = readl(data->membase + (bank * reg_width));
47 writel(reg, data->membase + (bank * reg_width));
89 int bank = id / (reg_width * BITS_PER_BYTE); local
93 reg = readl(data->membase + (bank * reg_width));
/linux-master/drivers/edac/
H A Dqcom_edac.c207 dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) argument
218 ret = regmap_read(drv->regmaps[bank], synd_reg,
227 ret = regmap_read(drv->regmaps[bank], regs.count_status_reg,
237 ret = regmap_read(drv->regmaps[bank], regs.ways_status_reg,
253 dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) argument
258 ret = dump_syn_reg_values(drv, bank, err_type);
264 edac_device_handle_ce(edev_ctl, 0, bank,
268 edac_device_handle_ue(edev_ctl, 0, bank,
272 edac_device_handle_ce(edev_ctl, 0, bank,
276 edac_device_handle_ue(edev_ctl, 0, bank,
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