1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Generic EP93xx GPIO handling
4 *
5 * Copyright (c) 2008 Ryan Mallon
6 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
7 *
8 * Based on code originally from:
9 *  linux/arch/arm/mach-ep93xx/core.c
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/slab.h>
18#include <linux/gpio/driver.h>
19#include <linux/bitops.h>
20#include <linux/seq_file.h>
21
22#define EP93XX_GPIO_F_INT_STATUS 0x5c
23#define EP93XX_GPIO_A_INT_STATUS 0xa0
24#define EP93XX_GPIO_B_INT_STATUS 0xbc
25
26/* Maximum value for gpio line identifiers */
27#define EP93XX_GPIO_LINE_MAX 63
28
29/* Number of GPIO chips in EP93XX */
30#define EP93XX_GPIO_CHIP_NUM 8
31
32/* Maximum value for irq capable line identifiers */
33#define EP93XX_GPIO_LINE_MAX_IRQ 23
34
35#define EP93XX_GPIO_A_IRQ_BASE 64
36#define EP93XX_GPIO_B_IRQ_BASE 72
37/*
38 * Static mapping of GPIO bank F IRQS:
39 * F0..F7 (16..24) to irq 80..87.
40 */
41#define EP93XX_GPIO_F_IRQ_BASE 80
42
43struct ep93xx_gpio_irq_chip {
44	u8 irq_offset;
45	u8 int_unmasked;
46	u8 int_enabled;
47	u8 int_type1;
48	u8 int_type2;
49	u8 int_debounce;
50};
51
52struct ep93xx_gpio_chip {
53	struct gpio_chip		gc;
54	struct ep93xx_gpio_irq_chip	*eic;
55};
56
57struct ep93xx_gpio {
58	void __iomem		*base;
59	struct ep93xx_gpio_chip	gc[EP93XX_GPIO_CHIP_NUM];
60};
61
62#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
63
64static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
65{
66	struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
67
68	return egc->eic;
69}
70
71/*************************************************************************
72 * Interrupt handling for EP93xx on-chip GPIOs
73 *************************************************************************/
74#define EP93XX_INT_TYPE1_OFFSET		0x00
75#define EP93XX_INT_TYPE2_OFFSET		0x04
76#define EP93XX_INT_EOI_OFFSET		0x08
77#define EP93XX_INT_EN_OFFSET		0x0c
78#define EP93XX_INT_STATUS_OFFSET	0x10
79#define EP93XX_INT_RAW_STATUS_OFFSET	0x14
80#define EP93XX_INT_DEBOUNCE_OFFSET	0x18
81
82static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
83					  struct ep93xx_gpio_irq_chip *eic)
84{
85	writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
86
87	writeb_relaxed(eic->int_type2,
88		       epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
89
90	writeb_relaxed(eic->int_type1,
91		       epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
92
93	writeb_relaxed(eic->int_unmasked & eic->int_enabled,
94		       epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
95}
96
97static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
98				     unsigned int offset, bool enable)
99{
100	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
101	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
102	int port_mask = BIT(offset);
103
104	if (enable)
105		eic->int_debounce |= port_mask;
106	else
107		eic->int_debounce &= ~port_mask;
108
109	writeb(eic->int_debounce,
110	       epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
111}
112
113static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
114{
115	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
116	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
117	struct irq_chip *irqchip = irq_desc_get_chip(desc);
118	unsigned long stat;
119	int offset;
120
121	chained_irq_enter(irqchip, desc);
122
123	/*
124	 * Dispatch the IRQs to the irqdomain of each A and B
125	 * gpiochip irqdomains depending on what has fired.
126	 * The tricky part is that the IRQ line is shared
127	 * between bank A and B and each has their own gpiochip.
128	 */
129	stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
130	for_each_set_bit(offset, &stat, 8)
131		generic_handle_domain_irq(epg->gc[0].gc.irq.domain,
132					  offset);
133
134	stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
135	for_each_set_bit(offset, &stat, 8)
136		generic_handle_domain_irq(epg->gc[1].gc.irq.domain,
137					  offset);
138
139	chained_irq_exit(irqchip, desc);
140}
141
142static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
143{
144	/*
145	 * map discontiguous hw irq range to continuous sw irq range:
146	 *
147	 *  IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
148	 */
149	struct irq_chip *irqchip = irq_desc_get_chip(desc);
150	unsigned int irq = irq_desc_get_irq(desc);
151	int port_f_idx = (irq & 7) ^ 4; /* {20..23,48..51} -> {0..7} */
152	int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
153
154	chained_irq_enter(irqchip, desc);
155	generic_handle_irq(gpio_irq);
156	chained_irq_exit(irqchip, desc);
157}
158
159static void ep93xx_gpio_irq_ack(struct irq_data *d)
160{
161	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
162	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
163	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
164	int port_mask = BIT(d->irq & 7);
165
166	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
167		eic->int_type2 ^= port_mask; /* switch edge direction */
168		ep93xx_gpio_update_int_params(epg, eic);
169	}
170
171	writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
172}
173
174static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
175{
176	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
177	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
178	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
179	int port_mask = BIT(d->irq & 7);
180
181	if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
182		eic->int_type2 ^= port_mask; /* switch edge direction */
183
184	eic->int_unmasked &= ~port_mask;
185	ep93xx_gpio_update_int_params(epg, eic);
186
187	writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
188	gpiochip_disable_irq(gc, irqd_to_hwirq(d));
189}
190
191static void ep93xx_gpio_irq_mask(struct irq_data *d)
192{
193	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
194	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
195	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
196
197	eic->int_unmasked &= ~BIT(d->irq & 7);
198	ep93xx_gpio_update_int_params(epg, eic);
199	gpiochip_disable_irq(gc, irqd_to_hwirq(d));
200}
201
202static void ep93xx_gpio_irq_unmask(struct irq_data *d)
203{
204	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
205	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
206	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
207
208	gpiochip_enable_irq(gc, irqd_to_hwirq(d));
209	eic->int_unmasked |= BIT(d->irq & 7);
210	ep93xx_gpio_update_int_params(epg, eic);
211}
212
213/*
214 * gpio_int_type1 controls whether the interrupt is level (0) or
215 * edge (1) triggered, while gpio_int_type2 controls whether it
216 * triggers on low/falling (0) or high/rising (1).
217 */
218static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
219{
220	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
221	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
222	struct ep93xx_gpio *epg = gpiochip_get_data(gc);
223	int offset = d->irq & 7;
224	int port_mask = BIT(offset);
225	irq_flow_handler_t handler;
226
227	gc->direction_input(gc, offset);
228
229	switch (type) {
230	case IRQ_TYPE_EDGE_RISING:
231		eic->int_type1 |= port_mask;
232		eic->int_type2 |= port_mask;
233		handler = handle_edge_irq;
234		break;
235	case IRQ_TYPE_EDGE_FALLING:
236		eic->int_type1 |= port_mask;
237		eic->int_type2 &= ~port_mask;
238		handler = handle_edge_irq;
239		break;
240	case IRQ_TYPE_LEVEL_HIGH:
241		eic->int_type1 &= ~port_mask;
242		eic->int_type2 |= port_mask;
243		handler = handle_level_irq;
244		break;
245	case IRQ_TYPE_LEVEL_LOW:
246		eic->int_type1 &= ~port_mask;
247		eic->int_type2 &= ~port_mask;
248		handler = handle_level_irq;
249		break;
250	case IRQ_TYPE_EDGE_BOTH:
251		eic->int_type1 |= port_mask;
252		/* set initial polarity based on current input level */
253		if (gc->get(gc, offset))
254			eic->int_type2 &= ~port_mask; /* falling */
255		else
256			eic->int_type2 |= port_mask; /* rising */
257		handler = handle_edge_irq;
258		break;
259	default:
260		return -EINVAL;
261	}
262
263	irq_set_handler_locked(d, handler);
264
265	eic->int_enabled |= port_mask;
266
267	ep93xx_gpio_update_int_params(epg, eic);
268
269	return 0;
270}
271
272/*************************************************************************
273 * gpiolib interface for EP93xx on-chip GPIOs
274 *************************************************************************/
275struct ep93xx_gpio_bank {
276	const char	*label;
277	int		data;
278	int		dir;
279	int		irq;
280	int		base;
281	bool		has_irq;
282	bool		has_hierarchical_irq;
283	unsigned int	irq_base;
284};
285
286#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
287	{							\
288		.label		= _label,			\
289		.data		= _data,			\
290		.dir		= _dir,				\
291		.irq		= _irq,				\
292		.base		= _base,			\
293		.has_irq	= _has_irq,			\
294		.has_hierarchical_irq = _has_hier,		\
295		.irq_base	= _irq_base,			\
296	}
297
298static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
299	/* Bank A has 8 IRQs */
300	EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ_BASE),
301	/* Bank B has 8 IRQs */
302	EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ_BASE),
303	EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
304	EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
305	EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
306	/* Bank F has 8 IRQs */
307	EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IRQ_BASE),
308	EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
309	EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
310};
311
312static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
313				  unsigned long config)
314{
315	u32 debounce;
316
317	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
318		return -ENOTSUPP;
319
320	debounce = pinconf_to_config_argument(config);
321	ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
322
323	return 0;
324}
325
326static void ep93xx_irq_print_chip(struct irq_data *data, struct seq_file *p)
327{
328	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
329
330	seq_printf(p, dev_name(gc->parent));
331}
332
333static const struct irq_chip gpio_eic_irq_chip = {
334	.name			= "ep93xx-gpio-eic",
335	.irq_ack		= ep93xx_gpio_irq_ack,
336	.irq_mask		= ep93xx_gpio_irq_mask,
337	.irq_unmask		= ep93xx_gpio_irq_unmask,
338	.irq_mask_ack	= ep93xx_gpio_irq_mask_ack,
339	.irq_set_type	= ep93xx_gpio_irq_type,
340	.irq_print_chip	= ep93xx_irq_print_chip,
341	.flags			= IRQCHIP_IMMUTABLE,
342	GPIOCHIP_IRQ_RESOURCE_HELPERS,
343};
344
345static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
346				struct platform_device *pdev,
347				struct ep93xx_gpio *epg,
348				struct ep93xx_gpio_bank *bank)
349{
350	void __iomem *data = epg->base + bank->data;
351	void __iomem *dir = epg->base + bank->dir;
352	struct gpio_chip *gc = &egc->gc;
353	struct device *dev = &pdev->dev;
354	struct gpio_irq_chip *girq;
355	int err;
356
357	err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
358	if (err)
359		return err;
360
361	gc->label = bank->label;
362	gc->base = bank->base;
363
364	girq = &gc->irq;
365	if (bank->has_irq || bank->has_hierarchical_irq) {
366		gc->set_config = ep93xx_gpio_set_config;
367		egc->eic = devm_kcalloc(dev, 1,
368					sizeof(*egc->eic),
369					GFP_KERNEL);
370		if (!egc->eic)
371			return -ENOMEM;
372		egc->eic->irq_offset = bank->irq;
373		gpio_irq_chip_set_chip(girq, &gpio_eic_irq_chip);
374	}
375
376	if (bank->has_irq) {
377		int ab_parent_irq = platform_get_irq(pdev, 0);
378
379		girq->parent_handler = ep93xx_gpio_ab_irq_handler;
380		girq->num_parents = 1;
381		girq->parents = devm_kcalloc(dev, girq->num_parents,
382					     sizeof(*girq->parents),
383					     GFP_KERNEL);
384		if (!girq->parents)
385			return -ENOMEM;
386		girq->default_type = IRQ_TYPE_NONE;
387		girq->handler = handle_level_irq;
388		girq->parents[0] = ab_parent_irq;
389		girq->first = bank->irq_base;
390	}
391
392	/* Only bank F has especially funky IRQ handling */
393	if (bank->has_hierarchical_irq) {
394		int gpio_irq;
395		int i;
396
397		/*
398		 * FIXME: convert this to use hierarchical IRQ support!
399		 * this requires fixing the root irqchip to be hierarchical.
400		 */
401		girq->parent_handler = ep93xx_gpio_f_irq_handler;
402		girq->num_parents = 8;
403		girq->parents = devm_kcalloc(dev, girq->num_parents,
404					     sizeof(*girq->parents),
405					     GFP_KERNEL);
406		if (!girq->parents)
407			return -ENOMEM;
408		/* Pick resources 1..8 for these IRQs */
409		for (i = 0; i < girq->num_parents; i++) {
410			girq->parents[i] = platform_get_irq(pdev, i + 1);
411			gpio_irq = bank->irq_base + i;
412			irq_set_chip_data(gpio_irq, &epg->gc[5]);
413			irq_set_chip_and_handler(gpio_irq,
414						 girq->chip,
415						 handle_level_irq);
416			irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
417		}
418		girq->default_type = IRQ_TYPE_NONE;
419		girq->handler = handle_level_irq;
420		girq->first = bank->irq_base;
421	}
422
423	return devm_gpiochip_add_data(dev, gc, epg);
424}
425
426static int ep93xx_gpio_probe(struct platform_device *pdev)
427{
428	struct ep93xx_gpio *epg;
429	int i;
430
431	epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
432	if (!epg)
433		return -ENOMEM;
434
435	epg->base = devm_platform_ioremap_resource(pdev, 0);
436	if (IS_ERR(epg->base))
437		return PTR_ERR(epg->base);
438
439	for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
440		struct ep93xx_gpio_chip *gc = &epg->gc[i];
441		struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
442
443		if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
444			dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
445				 bank->label);
446	}
447
448	return 0;
449}
450
451static struct platform_driver ep93xx_gpio_driver = {
452	.driver		= {
453		.name	= "gpio-ep93xx",
454	},
455	.probe		= ep93xx_gpio_probe,
456};
457
458static int __init ep93xx_gpio_init(void)
459{
460	return platform_driver_register(&ep93xx_gpio_driver);
461}
462postcore_initcall(ep93xx_gpio_init);
463
464MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
465		"H Hartley Sweeten <hsweeten@visionengravers.com>");
466MODULE_DESCRIPTION("EP93XX GPIO driver");
467MODULE_LICENSE("GPL");
468